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参数资料
型号： ADM1026
厂商： Analog Devices, Inc.
英文描述： Complete Thermal and System Management Controller
中文描述： 完整的热和系统管理控制器
文件页数： 43/56页
文件大小： 634K
代理商： ADM1026
ADM1026
Rev. A | Page 43 of 56
Table 38. Register 19h, Mask Register 2 (Power-On Default 00h)
Bit
Name
R/W
0
A
IN0
Mask = 0
R/W
1
A
IN1
Mask = 0
R/W
2
A
IN2
Mask = 0
R/W
3
A
IN3
Mask = 0
R/W
4
A
IN4
Mask = 0
R/W
5
A
IN5
Mask = 0
R/W
6
A
IN6
Mask = 0
R/W
7
A
IN7
Mask = 0
R/W
Description
When this bit is set, interrupts generated on the
A
IN0
voltage channel are masked out.
When this bit is set, interrupts generated on the
A
IN1
voltage channel are masked out.
When this bit is set, interrupts generated on the
A
IN2
voltage channel are masked out.
When this bit is set, interrupts generated on the
A
IN3
voltage channel are masked out.
When this bit is set, interrupts generated on the
A
IN4
voltage channel are masked out.
When this bit is set, interrupts generated on the
A
IN5
voltage channel are masked out.
When this bit is set, interrupts generated on the
A
IN6
voltage channel are masked out.
When this bit is set, interrupts generated on the
A
IN7
voltage channel are masked out.
Table 39. Register 1Ah, Mask Register 3 (Power-On Default 00h)
Bit
Name
R/W
0
FAN0 Mask = 0
R/W
1
FAN1 Mask = 0
R/W
2
FAN2 Mask = 0
R/W
3
FAN3 Mask = 0
R/W
4
FAN4 Mask = 0
R/W
5
FAN5 Mask = 0
R/W
6
FAN6 Mask = 0
R/W
7
FAN7 Mask = 0
R/W
Description
When this bit is set, interrupts generated on the
FAN0 tach channel are masked out.
When this bit is set, interrupts generated on the
FAN1 tach channel are masked out.
When this bit is set, interrupts generated on the
FAN2 tach channel are masked out.
When this bit is set, interrupts generated on the
FAN3 tach channel are masked out.
When this bit is set, interrupts generated on the
FAN4 tach channel are masked out.
When this bit is set, interrupts generated on the
FAN5 tach channel are masked out.
When this bit is set, interrupts generated on the
FAN6 tach channel are masked out.
When this bit is set, interrupts generated on the
FAN7 tach channel are masked out.
Table 40. Register 1Bh, Mask Register 4 (Power-On Default 00h)
Bit Name
R/W
0
Int Temp Mask = 0
R/W
1
V
BAT
Mask = 0
R/W
2
A
IN8
Mask = 0
R/W
3
THERM Mask = 0
R/W
4
AFC Mask = 0
R/W
5
Unused
R/W
6
CI Mask = 0
R/W
7
GPIO16 Mask = 0
R/W
Description
When this bit is set, interrupts generated on the internal temperature channel are masked out.
When this bit is set, interrupts generated on the V
BAT
voltage channel are masked out.
When this bit is set, interrupts generated on the A
IN8
voltage channel are masked out.
When this bit is set, interrupts generated from THERM events are masked out.
When this bit is set, interrupts generated from automatic fan control events are masked out.
Unused. Reads back 0.
When this bit is set, interrupts generated by the chassis intrusion input are masked out.
When this bit is set, interrupts generated on the GPIO16 channel are masked out.
Table 41. Register 1Ch, Mask Register 5 (Power-On Default 00h)
Bit
Name
R/W
0
GPIO0 Mask = 0
R/W
1
GPIO1 Mask = 0
R/W
2
GPIO2 Mask = 0
R/W
3
GPIO3 Mask = 0
R/W
4
GPIO4 Mask = 0
R/W
5
GPIO5 Mask = 0
R/W
6
GPIO6 Mask = 0
R/W
7
GPIO7 Mask = 0
R/W
Description
When this bit is set, interrupts generated on the
GPIO0 channel are masked out.
When this bit is set, interrupts generated on the
GPIO1 channel are masked out.
When this bit is set, interrupts generated on the
GPIO2 channel are masked out.
When this bit is set, interrupts generated on the
GPIO3 channel are masked out.
When this bit is set, interrupts generated on the
GPIO4 channel are masked out.
When this bit is set, interrupts generated on the
GPIO5 channel are masked out.
When this bit is set, interrupts generated on the
GPIO6 channel are masked out.
When this bit is set, interrupts generated on the
GPIO7 channel are masked out.
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