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参数资料
| 型号： | ADM1026JSTZ |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/55页 |
| 文件大小： | 0K |
| 描述： | IC CNTRL SYS REF/EEPROM 48LQFP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi Product Discontinuation 30/Sept/2011 |
| 标准包装： | 250 |
| 功能： | 硬件监控器 |
| 传感器类型： | 内部和外部 |
| 感应温度： | 0°C ~ 100°C |
| 精确度： | ±3°C（最小值） |
| 拓扑： | ADC，比较器，多路复用器，寄存器库 |
| 输出类型： | SMBus? |
| 输出警报： | 无 |
| 输出风扇： | 是 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | 0°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 1131 (CN2011-ZH PDF) |
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ADM1026
In the ADM1026, the write byte/word protocol is used for
four purposes. The ADM1026 knows how to respond by the
byte is the actual data. Bit 1 of EEPROM Register 3 must be
set. This is illustrated in Figure 22.
value of the command byte and EEPROM Register 3.
1
2
3
4
5
6
7
8
9 10
The first purpose is to write a single byte of data to RAM.
In this case, the command byte is the RAM address from 00h
to 6Fh and the (only) data byte is the actual data. This is
S
SLAVE
ADDRESS
W A
EEPROM
ADDRESS
HIGH BYTE
(80h TO 9Fh)
A
EEPROM
ADDRESS
LOW BYTE
(00h TO FFh)
A DATA
A
Y
illustrated in Figure 19.
Figure 22. Single-Byte Write to EEPROM
1
2
3
4
5
6
7 8
S
SLAVE
ADDRESS
W A
RAM
ADDRESS
(00h TO 6Fh)
A DATA A P
Block Write
In this operation, the master device writes a block of data
Figure 19. Single Byte Write to RAM
The protocol is also used to set up a 2-byte EEPROM
address for a subsequent read or block read. In this case, the
command byte is the high byte of the EEPROM address
from 80h to 9Fh. The (only) data byte is the low byte of the
EEPROM address. This is illustrated in Figure 20.
to a slave device. The start address for a block write must
have been set previously. In the case of the ADM1026, this
is done by a Send Byte operation to set a RAM address or by
a write byte/word operation to set an EEPROM address.
1. The master device asserts a start condition on the
SDA.
2. The master sends the 7-bit slave address followed
1
2
3
4
5
6
7
8
by the write bit (low).
S
SLAVE
ADDRESS
W A
EEPROM
ADDRESS
HIGH BYTE
(80h TO 9Fh)
A
EEPROM
ADDRESS
LOW BYTE
(00h TO FFh)
A P
3. The addressed slave device asserts an ACK on the
SDA.
4. The master sends a command code that tells the
Figure 20. Setting an EEPROM Address
If it is required to read data from the EEPROM
immediately after setting up the address, the master can
assert a repeat start condition immediately after the final
ACK and carry out a single-byte read or block read operation
without asserting an intermediate stop condition. In this
case, Bit 0 of EEPROM Register 3 should be set.
The third use is to erase a page of EEPROM memory.
EEPROM memory can be written to only if it is previously
erased. Before writing to one or more EEPROM memory
locations that are already programmed, the page or pages
containing those locations must first be erased. EEPROM
memory is erased by writing an EEPROM page address plus
an arbitrary byte of data with Bit 2 of EEPROM Register 3
set to 1.
Because the EEPROM consists of 128 pages of 64 bytes,
the EEPROM page address consists of the EEPROM
address high byte (from 80h to 9Fh) and the two MSBs of the
low byte. The lower six bits of the EEPROM address (low
byte only) specify addresses within a page and are ignored
slave device to expect a block write. The
ADM1026 command code for a block write is A0h
(10100000).
5. The slave asserts an ACK on the SDA.
6. The master sends a data byte (20h) that tells the
slave device that 32 data bytes are being sent to it.
The master should always send 32 data bytes to
the ADM1026.
7. The slave asserts an ACK on the SDA.
8. The master sends 32 data bytes.
9. The slave asserts an ACK on the SDA after each
data byte.
10. The master sends a packet error checking (PEC)
byte.
11. The ADM1026 checks the PEC byte and issues an
ACK if correct. If incorrect (NACK), the master
resends the data bytes.
12. The master asserts a stop condition on the SDA to
end the transaction.
W A A0h BLOCK A BYTE A DATA 1 A DATA 2 A DATA A PEC A
WRITE
during an erase operation.
1 2 3 4
5
6
7
8
9 10
S
SLAVE
ADDRESS
COMMAND
COUNT 32
P
ARBITRARY A Y
S
SLAVE
ADDRESS
W A
EEPROM
ADDRESS
HIGH BYTE
(80h TO 9Fh)
A
EEPROM
ADDRESS
LOW BYTE
(00h TO FFh)
A
DATA
Figure 23. Block Write to EEPROM or RAM
When performing a block write to EEPROM, Bit 1 of
Figure 21. EEPROM Page Erasure
Page erasure takes approximately 20 ms. If the EEPROM
is accessed before erasure is complete, the ADM1026
responds with No Acknowledge.
Last, this protocol is used to write a single byte of data to
EEPROM. In this case, the command byte is the high byte
of the EEPROM address from 80h to 9Fh. The first data byte
is the low byte of the EEPROM address, and the second data
EEPROM Register 3 must be set. Unlike some EEPROM
devices that limit block writes to within a page boundary,
there is no limitation on the start address when performing
a block write to EEPROM, except:
? There must be at least 32 locations from the start
address to the highest EEPROM address (9FF) to avoid
writing to invalid addresses.
? If the addresses cross a page boundary, both pages must
be erased before programming.
http://onsemi.com
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