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参数资料
| 型号： | ADM1041-EVAL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/64页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADM1041 |
| 标准包装： | 1 |
| 主要目的： | AC/DC，次级 |
| 输出及类型： | 1，非隔离 |
| 功率 - 输出： | 24W |
| 输出电压： | 12V |
| 电流 - 输出： | 2A |
| 输入电压： | 85 ~ 132VAC |
| 板类型： | 完全填充 |
| 已供物品： | 板，线缆，软件 |
| 已用 IC / 零件： | ADM1041 |
| 相关产品： | ADM1041AARQZ-REEL7-ND - IC SECONDARY SIDE CTRLR 24QSOP ADM1041ARQZ-REEL7TR-ND - IC SECONDARY SIDE CTRLR 24QSOP ADM1041AARQZ-REEL-ND - IC SECONDARY SIDE CTRLR 24QSOP ADM1041ARQZ-REEL-ND - IC SECONDARY SIDE CTRLR 24QSOP ADM1041AARQZ-ND - IC SECONDARY SIDE CTRLR 24QSOP ADM1041ARQZ-ND - IC PWR SUPP MON/LOAD SHAR 24QSOP ADM1041ARQ-REEL7-ND - IC PWR SUP MON/LOAD SHARE 24QSOP ADM1041ARQ-ND - IC PWR SUPP MON/LOAD SHAR 24QSOP |
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ADM1041
1
2
3
This specification is a measure of I DD during an EEPROM page erase cycle. The current is a dynamic. Refer to Figure 29 for a typical I DD plot during an EEPROM page
erase.
Specification is not production tested, but is supported by characterization data at initial product release.
Four external divider resistors are the same ration, which is selected to produce 2.0 V nominal at Pin 21 while at zero load current. Recommended values are
3.3 V
5.0 V
12 V
R TOP
R BOTTOM
680R
1K
1K.5
1K
5K1
1K
4
5
6
7
8
9
Chopper off.
The maximum specification here is the maximum source current of Pin 8 as specified by the Absolute Maximum Ratings.
All internal amplifiers accept inputs with common range from GND to V DD ? 2 V. The output is rail to rail but the input is limited to GND to V DD ? 2 V. See Figure 6.
These pins can be configured as open-drain N-channel or P-channel, (except PSON) and as normal or inverted logic polarity. Refer to Table 45.
A logic true or false is defined strictly according to the signal name. Low and high refer to the pin or signal voltages.
Endurance is qualified to 100,000 cycles as per JEDEC std. 22 method A117, and measured at ?40°C, +25°C, and +85°C. Typical endurance at 25°C is 250,000 cycles.
10
Retention lifetime equivalent at junction temperature (T J ) = 55°C as per JEDEC std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V. Derates
with junction temperature.
t LOW
t R
t F
t HD:STA
SCL
t HD:STA
t HD:DAT
t HIGH
t SU:DAT
t SU:STA
t SU:STO
SDA
t BUF
P
S
S
P
Figure 5. Serial Bus Timing Diagram
SHRO
SHRS+
SHRS–
VA
R1
VB
R1
VA = V DD – 0.4V
VB = V DD – 2V
R1 + R2 ≥ 1k ?
Figure 6. Amplifier Inputs and Outputs
Rev. A | Page 12 of 64
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