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参数资料
| 型号： | ADM1041-EVAL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/64页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADM1041 |
| 标准包装： | 1 |
| 主要目的： | AC/DC，次级 |
| 输出及类型： | 1，非隔离 |
| 功率 - 输出： | 24W |
| 输出电压： | 12V |
| 电流 - 输出： | 2A |
| 输入电压： | 85 ~ 132VAC |
| 板类型： | 完全填充 |
| 已供物品： | 板，线缆，软件 |
| 已用 IC / 零件： | ADM1041 |
| 相关产品： | ADM1041AARQZ-REEL7-ND - IC SECONDARY SIDE CTRLR 24QSOP ADM1041ARQZ-REEL7TR-ND - IC SECONDARY SIDE CTRLR 24QSOP ADM1041AARQZ-REEL-ND - IC SECONDARY SIDE CTRLR 24QSOP ADM1041ARQZ-REEL-ND - IC SECONDARY SIDE CTRLR 24QSOP ADM1041AARQZ-ND - IC SECONDARY SIDE CTRLR 24QSOP ADM1041ARQZ-ND - IC PWR SUPP MON/LOAD SHAR 24QSOP ADM1041ARQ-REEL7-ND - IC PWR SUP MON/LOAD SHARE 24QSOP ADM1041ARQ-ND - IC PWR SUPP MON/LOAD SHAR 24QSOP |
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ADM1041
In the ADM1041, the send byte protocol is used to write a
register address to RAM for a subsequent single-byte read from
the same address or block read or write starting at that address.
?
Set up a 2-byte EEPROM address for a subsequent read or
block read. In this case, the command byte is the high byte
of the EEPROM address (80h). The (only) data byte is the
low byte of the EEPROM address. This is illustrated in
1
2
3
4
5 6
S
SLAVE
ADDRESS
W A
RAM
ADDRESS
(00h TO 7Fh)
A P
1
S
2
SLAVE
ADDRESS
3
W A
4
EEPROM
ADDRESS
HIGH BYTE
5
A
6
EEPROM
ADDRESS
LOW BYTE
7 8
A P
(80h OR 81h)
(00h TO FFh)
Figure 30. Setting a RAM Address for Subsequent Read
Figure 32. Setting an EEPROM Address
If it is required to read data from the RAM immediately after
setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read, block read, or block write operation without
asserting an intermediate stop condition.
Write Byte/Word
If it is required to read data from the EEPROM immedi-
ately after setting up the address, the master can assert a
repeat start condition immediately after the final ACK and
carry out a single-byte read or a block read without
asserting an intermediate stop condition.
In this operation, the master device sends a command byte and
one or two data bytes to the slave device, as follows:
?
Write a single byte of data to EEPROM. In this case, the
command byte is the high byte of the EEPROM address,
80h or 81h. The first data byte is the low byte of the
1.
2.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
EEPROM address and the second data byte is the actual
data. Bit 1 of EEPROM Register 3 must be set. This is
1
2
3
4
5
6
7
8
9 10
3.
4.
The addressed slave device asserts ACK on SDA.
The master sends a command code.
S
SLAVE
ADDRESS
W A
EEPROM
ADDRESS
HIGH BYTE
(80h OR 81h)
A
EEPROM
ADDRESS
LOW BYTE
(00h TO FFh)
A
DATA
A P
5.
6.
7.
8.
9.
The slave asserts ACK on SDA.
The master sends a data byte.
The slave asserts ACK on SDA.
The master sends a data byte (or may assert stop at this
point).
The slave asserts ACK on SDA.
Figure 33. Single-Byte Write to EEPROM
If it is required to read data from the ASIC immediately after
setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read, block read, or block write operation without
asserting an intermediate stop condition.
Block Write
In this operation, the master device writes a block of data to a
10. The master asserts a stop condition on SDA to end the
transaction.
In the ADM1041, the write byte/word protocol is used for the
following three purposes. The ADM1041 knows how to respond
by the value of the command byte.
slave device. Programming an EEPROM byte takes approximately
300 μs, which limits the SMBus clock for repeated or block write
operations. The start address for a block write must have been
set previously. In the case of the ADM1041, this is done by a
send byte operation to set a RAM address or by a write byte/
word operation to set an EEPROM address.
?
Write a single byte of data to RAM. In this case, the
command byte is the RAM address from 00h to 7Fh and
the (only) data byte is the actual data. This is illustrated in
1.
2.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
1
S
2
SLAVE
ADDRESS
3
W A
4
RAM
ADDRESS
(00h TO 7Fh)
5
A
6
DATA
7 8
A P
3.
4.
The addressed slave device asserts ACK on SDA.
The master sends a command code that tells the slave
device to expect a block write. The ADM1041 command
Figure 31. Single-Byte Write to RAM
5.
Rev. A | Page 37 of 64
code for a block read is A0h (10100000).
The slave asserts ACK on SDA.
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