参数资料
型号: ADM1168ASTZ
厂商: Analog Devices Inc
文件页数: 16/28页
文件大小: 0K
描述: IC SEQUENCER/SUPERVISOR 32LQFP
标准包装: 1
系列: Super Sequencer®
应用: 电源监控器,序列发生器
输入电压: 3 V ~ 14.4 V
电源电压: 3 V ~ 14.4 V
电流 - 电源: 4.2mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 托盘
ADM1168
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 21 shows how the simple building block of a single
SE state can be used to build a power-up sequence for a three-
supply system. Table 8 lists the PDO outputs for each state in
the same SE implementation. In this system, a good 5 V supply
on the VP1 pin and the VX1 pin held low are the triggers required
to start a power-up sequence. The sequence next turns on the 3.3 V
supply, then the 2.5 V supply (assuming successful turn on of the
3.3 V supply). When all three supplies have turned on correctly,
the PWRGD state is entered, where the SE remains until a fault
occurs on one of the three supplies or until it is instructed to go
through a power-down sequence by VX1 going high.
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following three sections (the Sequence
Detector section, the Monitoring Fault Detector section, and
Data Sheet
If a timer delay is specified, the input to the sequence detector
must remain in the defined state for the duration of the timer
delay. If the input changes state during the delay, the timer is reset.
The sequence detector can also help to identify monitoring faults.
In the sample application shown in Figure 21, the FSEL1 and
FSEL2 states first identify which of the VP1, VP2, or VP3 pins
has faulted, and then they take appropriate action.
SEQUENCE
STATES
IDLE1
VX1 = 0
IDLE2
the Timeout Detector section) describe the individual blocks
and use the sample application shown in Figure 21 to demonstrate
the actions of the state machine.
Sequence Detector
The sequence detector block is used to detect when a step in a
MONITOR FAULT
STATES
VP1 = 0
VP1 = 1
EN3V3
10ms
VP2 = 1
TIMEOUT
STATES
sequence has been completed. It looks for one of the SE inputs
to change state and is most often used as the gate for successful
progress through a power-up or power-down sequence. A timer
(VP1 + VP2) = 0
EN2V5
20ms
DIS3V3
VX1 = 1
block that is included in this detector can insert delays into a
VP3 = 1
power-up or power-down sequence, if required. Timer delays
can be set from 10 μs to 400 ms. Figure 20 is a block diagram
of the sequence detector.
(VP1 + VP2 + VP3) = 0
PWRGD
VP2 = 0
DIS2V5
VX1 = 1
VP1
SUPPLY FAULT
DETECTION
SEQUENCE
(VP1 +
VP2) = 0
FSEL1
VX1 = 1
DETECTOR
VP3 = 0
VX4
LOGIC INPUT CHANGE
OR FAULT DETECTION
TIMER
VP1 = 0
FSEL2
VP2 = 0
WARNINGS
INVERT
FORCE FLOW
(UNCONDITIONAL JUMP)
SELECT
Figure 20. Sequence Detector Block Diagram
Table 8. PDO Outputs for Each State
Figure 21. Sample Application Flow Diagram
PDO Outputs
PDO1 = 3V3ON
PDO2 = 2V5ON
PDO3 = FAULT
IDLE1
0
0
0
IDLE2
0
0
0
EN3V3
1
0
0
EN2V5
1
1
0
DIS3V3
0
1
1
DIS2V5
1
0
1
PWRGD
1
1
0
FSEL1
1
1
1
FSEL2
1
1
1
Rev. A | Page 16 of 28
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