参数资料
型号: ADM1175-1ARMZ-R7
厂商: Analog Devices Inc
文件页数: 12/24页
文件大小: 0K
描述: IC CTRLR HOTSWAP 16.5V 10-MSOP
产品培训模块: Hot Swap Design
标准包装: 1
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: 3.15 V ~ 16.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 标准包装
产品目录页面: 792 (CN2011-ZH PDF)
配用: EVAL-ADM1175EBZ-ND - BOARD EVALUATION FOR ADM1175
其它名称: ADM1175-1ARMZ-R7DKR

ADM1175
OVERVIEW OF THE HOT SWAP FUNCTION
When circuit boards are inserted into a live backplane, discharged
supply bypass capacitors draw large transient currents from the
backplane power bus as they charge. Such transient currents can
cause permanent damage to connector pins, as well as dips on
the backplane supply that can reset other boards in the system.
The ADM1175 is designed to turn a circuit board supply voltage
on and off in a controlled manner, allowing the circuit board to
be safely inserted into or removed from a live backplane. The
ADM1175 can reside either on the backplane or on the circuit
board itself.
The ADM1175 controls the inrush current to a fixed maximum
level by modulating the gate of an external N-channel FET placed
between the live supply rail and the load. This hot swap function
protects the card connectors and the FET itself from damage
and limits any problems that can be caused by high current loads
on the live supply rail.
The ADM1175 holds the GATE pin down (and therefore holds
off the FET) until certain conditions are met. An undervoltage
lockout circuit ensures that the device is provided with an adequate
input supply voltage. After the input supply voltage is successfully
detected, the device goes through an initial timing cycle to provide
a delay before it attempts to hot swap. This delay ensures that
the board is fully seated in the backplane before the board is
powered up.
After the initial timing cycle is complete, the hot swap function
is switched on under control of the ON/ONB pin. When ON/ONB
is asserted (high for the ADM1175-1 and ADM1175-2, low for
the ADM1175-3 and ADM1175-4), the hot swap operation starts.
The ADM1175 charges up the gate of the FET to turn on the
load. It continues to charge up the GATE pin until the linear
current limit (set to 100 mV/R SENSE ) is reached. For some combi-
nations of low load capacitance and high current limit, this limit
may not be reached before the load is fully charged up. If the
current limit is reached, the ADM1175 regulates the GATE pin
to keep the current at this limit. For currents above the overcur-
rent fault timing threshold, nominally 100 mV/R SENSE , the
current fault is timed by sourcing a current out to the TIMER
pin. If the load becomes fully charged before the fault current
limit time is reached (when the TIMER pin reaches 1.3 V), the
current drops below the overcurrent fault timing threshold.
The ADM1175 then charges the GATE pin higher to fully
enhance the FET for lowest R ON , and the TIMER pin is pulled
down again.
If the fault current limit time is reached before the load drops
below the current limit, a fault has been detected, and the hot
swap operation is aborted by pulling down the GATE pin to
turn off the FET.
Data Sheet
The ADM1175-2 and ADM1175-4 are latched off. They attempt
to hot swap again only when the ON/ONB pin is deasserted and
then asserted again. The ADM1175-1 and ADM1175-3 retry
the hot swap operation indefinitely, keeping the FET in its safe
operating area (SOA) by using the TIMER pin to time a cool-
down period between hot swap attempts. The current and voltage
threshold combinations on the TIMER pin set the retry duty cycle
to 3.8%.
The ADM1175 is designed to operate over a range of supplies
from 3.15 V to 16.5 V.
UNDERVOLTAGE LOCKOUT
An internal undervoltage lockout (UVLO) circuit resets the
ADM1175 if the voltage on the VCC pin is too low for normal
operation. The UVLO has a low-to-high threshold of 2.8 V, with
80 mV hysteresis. Above 2.8 V supply voltage, the ADM1175
starts the initial timing cycle.
ON/ONB FUNCTION
The ADM1175-1 and ADM1175-2 have an active high ON pin.
The ON pin is the input to a comparator that has a low-to-high
threshold of 1.3 V, a 50 mV hysteresis, and a glitch filter of 3 μs.
A low input on the ON pin turns off the hot swap operation by
pulling the GATE pin to ground, turning off the external FET.
The TIMER pin is also reset by turning on a pull-down current
on this pin. A low-to-high transition on the ON pin starts the
hot swap operation. A 10 kΩ pull-up resistor connecting the
ON pin to the supply is recommended.
Alternatively, an external resistor divider at the ON pin can be
used to program an undervoltage lockout value that is higher
than the internal UVLO circuit, thereby setting the hot swap
operation to start on specific voltage level on the VCC pin. An
RC filter can be added at the ON pin to increase the delay time
at card insertion if the initial timing cycle delay is insufficient.
The ADM1175-3 and ADM1175-4 have an active low ONB pin.
This pin operates exactly as described above for the ON pin,
but the polarity is reversed. This allows this pin to function as
an overvoltage detector that can use the external FET as a circuit
breaker for overvoltage conditions on the monitored supply.
TIMER FUNCTION
The TIMER pin handles several timing functions with an
external capacitor, C TIMER . There are two comparator thresholds:
V TIMERH (1.3 V) and V TIMERL (0.2 V). The four timing current
sources are a 5 μA pull-up, a 60 μA pull-up, a 2 μA pull-down,
and a 100 μA pull-down. The 100 μA pull-down is a nonideal
current source, approximating a 7 kΩ resistor below 0.4 V.
These current and voltage levels, together with the value of C TIMER
chosen by the user, determine the initial timing cycle time, the
fault current limit time, and the hot swap retry duty cycle.
Rev. C | Page 12 of 24
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