参数资料
型号: ADM1178-2ARMZ-R7
厂商: Analog Devices Inc
文件页数: 6/24页
文件大小: 0K
描述: IC CTRLR HOTSWAP 16.5V 10-MSOP
产品培训模块: Hot Swap Design
标准包装: 1
类型: 热交换控制器
应用: 通用
内部开关:
电流限制: 可调
电源电压: 3.15 V ~ 16.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 标准包装
产品目录页面: 792 (CN2011-ZH PDF)
配用: EVAL-ADM1178EBZ-ND - BOARD EVALUATION FOR ADM1178
其它名称: ADM1178-2ARMZ-R7DKR

ADM1178
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
VCC 1
10 ALERTB
SENSE 2
ON 3
GND 4
TIMER 5
ADM1178
TOP VIEW
(Not to Scale)
9
8
7
6
GATE
ADR
SDA
SCL
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
VCC
SENSE
ON
GND
TIMER
SCL
SDA
ADR
GATE
ALERTB
Description
Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V. An undervoltage
lockout (UVLO) circuit resets the ADM1178whenalowsupplyvoltageisdetected.
Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin sets the analog current
limit. The hot swap operation of the ADM1178 controls the external FET gate to maintain the (V CC ? V SENSE )
voltage at or below 100 mV.
Undervoltage Input Pin. Active high pin. An internal undervoltage comparator has a trip threshold of 1.3 V,
and the output of this comparator is used as an enable for the hot swap operation. With an external resistor
divider from VCC to GND, the ON pin can be used to enable the hot swap operation for a specific voltage on
VCC, providing an undervoltage function.
Chip Ground Pin.
Timer Pin. An external capacitor, C TIMER , sets a 270 ms/μF initial timing cycle delay and a 21.7 ms/μF fault delay.
The GATE pin turns off when the TIMER pin is pulled beyond the upper threshold. An overvoltage detection
with an external Zener can be used to force this pin high.
I 2 C Clock Pin. Open-drain input requires an external resistive pull-up.
I 2 C Data I/O Pin. Open-drain input/output. Requires an external resistive pull-up.
I 2 C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four I 2 C
addresses.
GATE Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the
FET drive controller, which utilizes a charge pump to provide a 12.5 μA pull-up current to charge the FET
GATE pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor)
by modulating the GATE pin.
Alert Output Pin. Active low, open-drain configuration. This pin asserts when an overcurrent condition is
present. The overcurrent level that causes an alert to be asserted is digitally programmable via the I 2 C
interface. This function can also be enabled/disabled via I 2 C.
Rev. D | Page 6 of 24
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