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参数资料
| 型号： | ADM1192ARMZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC PWR MONITOR DGTL ALERT 10MSOP |
| 标准包装： | 1 |
| 应用： | 监控，数字电流 |
| 电流 - 电源： | 1.7mA |
| 电源电压： | 3.15 V ~ 26 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 标准包装 |
| 配用： | EVAL-ADM1192EBZ-ND - BOARD EVALUATION FOR ADM1192 |
| 其它名称： | ADM1192ARMZ-R7DKR |
Data Sheet
ADM1192
WRITE EXTENDED COMMAND BYTE
In the write extended command byte operation, the master
device writes to one of the three extended registers of the slave
device, as follows:
7.
8.
The slave asserts an acknowledge on SDA.
The master asserts a stop condition on SDA to end the
transaction.
SLAVE
REGISTER
1.
2.
3.
4.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address, followed by the
write bit (low).
The addressed slave device asserts an acknowledge on SDA.
The master sends the register address byte. The MSB of this
byte is set to 1 to indicate an extended register write. The two
LSBs indicate which of the three extended registers are to be
written to (see Table 8). All other bits should be set to 0.
The slave asserts an acknowledge on SDA.
The master sends the extended command byte (refer to
1 2 3 4 5 6 7 8
EXTENDED
S ADDRESS W A ADDRESS A COMMAND A P
BYTE
Figure 23. Write Extended Byte
extended register.
Table 8. Extended Register Addresses
A6 A5 A4 A3 A2 A1 A0 Extended Register
0 0 0 0 0 0 1 ALERT_EN
0 0 0 0 0 1 0 ALERT_TH
0
0
0
0
0
1
1
CONTROL
Table 9. ALERT_EN Register Operations
Bit
0
1
2
3
Default
0
0
1
0
Name
EN_ADC_OC1
EN_ADC_OC4
EN_OC_ALERT
EN_OFF_ALERT
Function
LSB, enabled if a single ADC conversion on the I channel exceeds the threshold set in the ALERT_TH register.
Enabled if four consecutive ADC conversions on the I channel exceed the threshold set in the
ALERT_TH register.
Enables the OC_ALERT register. If an overcurrent condition is present compared to the SETV threshold, and
the TIMER pin charges to 1.3 V, the OC_ALERT register captures and latches this condition.
Enables an alert if the hot swap operation is turned off by an operation that writes the SWOFF bit high.
This allows a software override of the ALERT output and turns on a P-channel FET controlled by ALERT.
4
0
CLEAR
Clears the OC_ALERT and ADC_ALERT status bits in the status register. The value of these bits can
immediately change if the source of the alert is not cleared and the alert function is not disabled.
The CLEAR bit self-clears to 0 after the STATUS register bits are cleared.
Table 10. ALERT_TH Register Operations
Bit
[7:0]
Default
FF
Function
The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit
value corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit
0
Default
0
Name
SWOFF
Function
LSB, forces the ALERT pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).
Rev. D | Page 13 of 20
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