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参数资料
| 型号： | ADM1192ARMZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/20页 |
| 文件大小： | 0K |
| 描述： | IC PWR MONITOR DGTL ALERT 10MSOP |
| 标准包装： | 1 |
| 应用： | 监控，数字电流 |
| 电流 - 电源： | 1.7mA |
| 电源电压： | 3.15 V ~ 26 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 标准包装 |
| 配用： | EVAL-ADM1192EBZ-ND - BOARD EVALUATION FOR ADM1192 |
| 其它名称： | ADM1192ARMZ-R7DKR |
ADM1192
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
VCC 1
10 ALERT
SENSE 2
SETV 3
GND 4
TIMER 5
ADM1192
TOP VIEW
(Not to Scale)
9
8
7
6
CLRB
ADR
SDA
SCL
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
VCC
SENSE
SETV
GND
TIMER
SCL
SDA
ADR
CLRB
ALERT
Description
Positive Supply Input Pin. The operating supply voltage range is 3.15 V to 26 V. An undervoltage lockout (UVLO)
circuit resets the ADM1192 when a low supply voltage is detected.
Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin generates a voltage across
a sense resistor. This voltage is proportional to the load current. A current sense amplifier amplifies this
voltage before it is digitized by the ADC.
Input Pin. The voltage driven onto this pin is compared with the output of the internal current sense amplifier.
The lower the voltage on the SETV, the lower the current level that causes the ALERT output to assert. Typical
response time is 1 μs to 2 μs.
Chip Ground Pin.
Timer Input Pin. An external capacitor, C TIMER , sets the timing period for masking overcurrent conditions. This
timing period should be sufficient to allow the inrush current to completely charge up the load without
tripping an overcurrent fault. This makes the device robust against false triggering due to current transients.
I 2 C Clock Pin. Open-drain input; requires an external resistive pull-up.
I 2 C Data I/O Pin. Open-drain input/output; requires an external resistive pull-up.
I 2 C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four I 2 C
addresses.
Clear Pin. A latched overcurrent condition can be cleared by toggling this pin low. Holding this pin low
disables the ALERT output.
Alert Output Pin. Active high, open-drain configuration. This pin asserts high when an overcurrent condition is
present. The level at which an overcurrent condition is detected depends on either the voltage on the SETV pin or
the value in the ALERT_TH register. The ALERT_EN register determines which is used in the comparison. This pin has
a latching function and must be cleared manually using either the ALERT_EN register or the CLRB pin.
Rev. D | Page 6 of 20
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