参数资料
| 型号： | ADM3251EARWZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC TXRX RS232 ISOLATED 20-SOIC |
| 产品培训模块： | Power Line Monitoring iCoupler Digital Isolater Technology |
| 标准包装： | 37 |
| 类型： | 线路收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | RS232 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 管件 |
| 配用： | EVAL-ADM3251EEB1Z-ND - BOARD EVALUATION FOR ADM3251 EVAL-ADM3251EEBZ-ND - BOARD EVALUATION ADM3251 |
Data Sheet
ADM3251E
APPLICATIONS INFORMATION
PCB LAYOUT
The ADM3251E requires no external circuitry for its logic
interfaces. Power supply bypassing is required at the input and
output supply pins (see Figure 21). Bypass capacitors are
conveniently connected between Pin 3 and Pin 4 for VCC and
between Pin 19 and Pin 20 for VISO. The capacitor value should
be between 0.01 μF and 0.1 μF. The total lead length between
both ends of the capacitor and the input power supply pin
should not exceed 20 mm.
Because it is not possible to apply a heat sink to an isolation
device, the device primarily depends on heat dissipating into
the PCB through the ground pins. If the device is used at high
ambient temperatures, care should be taken to provide a
thermal path from the ground pins to the PCB ground plane.
The board layout in Figure 21 shows enlarged pads for Pin 4,
Pin5, Pin 6, Pin 7, Pin 10, and Pin 11. Multiple vias should be
implemented from each of the pads to the ground plane, which
significantly reduce the temperatures inside the chip. The
dimensions of the expanded pads are left to the discretion of the
designer and the available board space.
NC
VCC
GND
VISO
V+
C1+
C1–
GND
TOUT
GND
RIN
GND
C2+
ROUT
C2–
TIN
V–
GND
GNDISO
07388-
018
ADM3251E
VIA TO GNDISO
0.1F
C3
C1
C2
0.1F
NC = NO CONNECT
C4
Figure 21. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients,
care should be taken to ensure that board coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed such that any coupling that does occur
equally affects all pins on a given component side.
The power supply section of the ADM3251E uses a 300 MHz
oscillator frequency to pass power through its chip-scale trans-
formers. Operation at these high frequencies may raise concerns
about radiated emissions and conducted noise. PCB layout and
construction is a very important tool for controlling radiated
emissions. Refer to Application Note AN-0971, Control of
Radiated Emissions with isoPower Devices, for extensive guidance
on radiation mechanisms and board layout considerations.
EXAMPLE PCB FOR REDUCED EMI
The choice of how aggressively EMI must be addressed for a
design to pass emissions levels depends on the requirements of
the design as well as cost and performance trade-offs.
The starting point for this example is a 2-layer PCB. EMI reduc-
tions are relative to the emissions and noise from this board. To
conform to FCC Class B levels, the emissions at these two
frequencies must be less than 46 dBμV/m, normalized to 3 m
antenna distance. As expected, EMI testing confirmed that the
largest emissions peaks occur at the tank frequency and rectifier
frequency.
A 6-layer PCB that employs edge guarding and buried capacitive
bypassing, which are EMI mitigation techniques described in
detail in Application Note AN-0971, was manufactured. The
stackup of the 6-layer test PCB is shown in Table 9. PCB layout
Gerber files are available upon request.
Table 9. PCB Layers
Layer
Description
Top
Components and ground planes
Inner Layer 1
VCC planes
Inner Layer 2
All tracks
Inner Layer 3
Blank
Inner Layer 4
Buried capacitive plane
Bottom
Ground planes
EMI testing was repeated on the optimized board. The resulting
reduction in radiated emissions is shown in Table 10. This
board meets FCC Class B standards with no external shielding
by utilizing buried stitching capacitors and edge fencing.
Table 10. EMI Test Results
EMI Test Results
300 MHz
600 MHz
2-Layer PCB Emissions
48 dB
53 dB
6-Layer PCB Emissions
36 dB
32 dB
Achieved EMI Reduction
12 dB
21 dB
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the trans-
former. The decoder is bistable and is, therefore, either set or
reset by the pulses, indicating input logic transitions.
In the absence of logic transitions at the input for more than
1 μs, periodic sets of refresh pulses (indicative of the correct
input state) are sent to ensure dc correctness at the output. If the
decoder receives no internal pulses for more than approximately
5 μs, the input side is assumed to be unpowered or nonfunctional,
in which case the isolator output is forced to a default state by
the watchdog timer circuit. This situation should occur in the
ADM3251E during power-up and power-down operations only.
Rev. G | Page 13 of 16
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