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| 型号： | ADM690AN |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/16页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU 4.65 WD 8DIP |
| 标准包装： | 50 |
| 类型： | 备用电池电路 |
| 监视电压数目： | 1 |
| 输出： | 推挽式，图腾柱 |
| 复位： | 低有效 |
| 复位超时： | 最小为 35 ms |
| 电压 - 阀值： | 4.65V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
ADM690–ADM695
Table I. ADM691, ADM693, ADM695 Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period
Immediately
Reset Active Period
OSC SEL
OSC IN
Normal After Reset
ADM691/ADM693
ADM695
Low
Low
Floating or High
Floating or High
External Clock Input
External Capacitor
Low
Floating or High
1024 CLKS
260 ms × C/47 pF
100 ms
1.6 s
4096 CLKS
1.04 s × C/47 pF
1.6 s
1.6 s
512 CLKS
130 ms × C/47 pF
50 ms
50 ms
2048 CLKS
520 ms × C/47 pF
200 ms
200 ms
NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF).
The watchdog timeout period is fixed at 1.6 seconds, and the
reset pulse width is fixed at 50 ms on the ADM690/ADM692.
On the ADM694 the watchdog timeout period is also 1.6 sec-
onds but the reset pulse width is fixed at 200 ms. The ADM691/
ADM693/ADM695 allow these times to be adjusted as shown
in Table I. Figure 4 shows the various oscillator configurations
8
OSC SEL
ADM691
ADM693
ADM695
which can be used to adjust the reset pulse width and watchdog
timeout period.
C OSC
7
OSC IN
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
Figure 4b. External Capacitor
either case, immediately after a reset, the timeout period is 1.6
seconds. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period be-
comes effective after the first transition of WDI. The software
should be written such that the I/O port driving WDI is left in
NC
8
OSC SEL
ADM691
ADM693
ADM695
its power-up reset state until the initialization routines are com-
pleted and the microprocessor is able to toggle WDI at the mini-
NC
7
OSC IN
mum watchdog timeout period of 70 ms.
Watchdog Output (WDO)
The Watchdog Output WDO (ADM691/ADM693/ADM695)
provides a status output which goes low if the watchdog timer
“times out” and remains low until set high by the next transition
Figure 4c. Internal Oscillator (1.6 Second Watchdog)
on the Watchdog Input. WDO is also set high when V CC goes
below the reset threshold.
8
OSC SEL
NC
8
OSC SEL
ADM691
ADM693
ADM695
ADM691
ADM693
7
CLOCK
ADM695
OSC IN
0 TO 250kHz
7
OSC IN
Figure 4d. Internal Oscillator (100 ms Watchdog)
Figure 4a. External Clock Source
REV. A
–7 –
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