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| 型号： | ADM691ARZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/12页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU 4.65V 16SOIC |
| 标准包装： | 400 |
| 类型： | 备用电池电路 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极，推挽式 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 35 ms |
| 电压 - 阀值： | 4.65V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
| 其它名称： | ADM691ARZ-REEL7TR |
ADM691A/ADM693A/ADM800L/M
100
90
10
0%
100
90
10
0%
1V
400ms
1V
10μs
Figure 14. RESET Output Voltage vs. Supply
POWER FAIL RESET OUTPUT
RESET is an active low output that provides a reset signal to the
Microprocessor whenever V CC is at an invalid level. When V CC
falls below the reset threshold, the RESET output is forced
low. The reset voltage threshold is 4.65 V (ADM691A/
ADM800L) or 4.4 V (ADM693A/ADM800M).
On power-up RESET will remain low for 200 milliseconds after
V CC rises above the appropriate reset threshold. This allows time
for the power supply and microprocessor to stabilize. On power-
down, the RESET output remains low with V CC as low as 1 V.
This ensures that the microprocessor is held in a stable shut-
down condition. If RESET is required to be low for voltages be-
low 1 V, this may be achieved by connecting a pull-down resistor
Figure 15. RESET Response Time
The normal (short) timeout period becomes effective following
the first transition of WDI after reset has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 seconds). The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI). If floating, an internal resistor network biases WDI to
around 1.6 V.
BATT ON
on the RESET line. The resistor will help maintain RESET low
down to V CC = 0 V. Note that this is only necessary if V BATT is
below 2 V. With battery voltages ≥ 2 V RESET will function cor-
rectly with V CC from 0 V to +5.5 V.
V CC
4.65V 1
LOW LINE
V OUT
This reset active time is adjustable by using an external oscillator
or by connecting an external capacitor to the OSC IN pin. Refer
to Table II.
V BATT
CHIP ENABLE
OUTPUT
CONTROL
The guaranteed minimum and maximum thresholds of the
ADM691A/ADM800L are 4.5 V and 4.75 V, while the guaran-
teed thresholds of the ADM693A/ADM800M are 4.25 V and
CE IN
CE OUT
RESET &
GENERATOR
4.5 V. The ADM691A/ADM800L is therefore compatible with
5 V supplies with a +10%, –5% tolerance while the ADM693A/
ADM800M is compatible with 5 V ± 10% supplies.
In addition to RESET an active high RESET output is provided.
This is the complement of RESET and is useful for processors
requiring an active high RESET signal.
Watchdog Timer Reset
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
OSC IN
OSC SEL
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
RESET &
WATCHDOG
TIMEBASE
WATCHDOG WATCHDOG
TRANSITION DETECTOR TIMER
1.25V
ADM691A/ADM693A
ADM800L/ADM800M
1 VOLTAGE
DETECTOR = 4.4V (ADM693A/ADM800M)
RESET
RESET
WATCHDOG
OUTPUT ( WDO )
POWER FAIL
OUTPUT ( PFO )
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a reset pulse is generated. The watch-
dog timeout period may be configured for either a fixed “short”
100 ms or a “long” 1.6 second timeout period or for an adjust-
able timeout period. Note that even if the short timeout period
is selected, the first time out immediately following a reset is
1.6 sec. This is to allow additional time for the microprocessor
to regain control following a reset.
The watchdog timer is restarted at the end of reset, whether the
reset was caused by lack of activity on WDI or by V CC falling be-
low the reset threshold.
REV. 0
Figure 16. Functional Block Diagram
Watchdog Output ( WDO )
The Watchdog Output WDO provides a status output that goes
low if the watchdog timer “times out” and remains low until set
high by the next transition on the watchdog input. WDO is also
set high when V CC goes below t he reset threshold. If WDI re-
mains high or low indefinitely, RESET and RESET will gener-
ate 200 ms pulses every 1.6 sec.
–7 –
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