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| 型号： | ADM691ARZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU 4.65V 16SOIC |
| 标准包装： | 400 |
| 类型： | 备用电池电路 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极，推挽式 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 35 ms |
| 电压 - 阀值： | 4.65V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
| 其它名称： | ADM691ARZ-REEL7TR |
ADM691A/ADM693A/ADM800L/M
8
OSC SEL
INPUT
POWER
7
OSC IN
ADM69_A
ADM800_
R1
R2
POWER
FAIL
INPUT
1.25V
PFO
POWER
FAIL
OUTPUT
C OSC
Figure 18d. Internal Oscillator (100 ms Watchdog)
Figure 20. Power Fail Comparator
Table III. Input and Output Status in Battery Backup Mode
WDI
Signal
Status
WDO
V BATT
V OUT
V CC
Supply Current is <1 μ A.
V OUT is connected to V BATT via an internal
PMOS switch.
Switchover comparator monitors V CC for
RESET
t 2
t 3
GND
BATT ON
active switchover.
0 V.
Logic High. The open circuit voltage is equal
to V OUT .
t 1
t 1
t 1
LOW LINE
OSC IN
Logic Low.
OSC IN is ignored.
t 1 = RESET TIME.
t 2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.
t 3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.
Figure 19. Watchdog Timing
CE Gating and RAM Write Protection
All products include memory protection circuitry which ensures
the integrity of data in memory by preventing write operations
when V CC is at an invalid level. There are two additional pins,
CE IN and CE OUT , that control the Chip Enable or Write inputs
of CMOS RAM. When V CC is present, CE OUT is a buffered rep-
lica of CE IN , with a 5 ns propagation delay. When V CC falls be-
low the reset voltage threshold, an internal gate forces CE OUT
high, independent of CE IN .
CE OUT typically drives the CE, CS, or Write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V CC is at an in-
valid level. Similar protection of EEPROMs can be achieved by
using the CE OUT to drive the Store or Write inputs of an
EEPROM, EAROM, or NOVRAM.
Power Fail Warning Comparator
An additional comparator is provided for early warning of fail-
ure in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.25 V reference. The Power
Fail Output ( PFO ) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider that
senses either the unregulated dc input to the system’s 5 V regu-
lator or the regulated 5 V output. The voltage divider ratio can
be chosen such that the voltage at PFI falls below 1.25 V several
milliseconds before the +5 V power supply falls below the reset
threshold. PFO is normally used to interrupt the microprocessor
so that data can be stored in RAM and the shut- down proce-
dure executed before power is lost.
REV. 0
OSC SEL
PFI
PFO
WDI
CE OUT
CE IN
WDO
RESET
RESET
–9 –
OSC SEL is ignored.
The Power Fail Comparator remains active in
the battery-backup mode for V CC ≥ V BATT
–1.2 V. With V CC lower than this, PFO is
forced low.
The Power Fail Comparator remains active in
the battery-backup mode for V CC ≥ V BATT
–1.2 V. With V CC lower than this, PFO is
forced low.
WDI is ignored.
Logic High. The open circuit voltage is equal
to V OUT .
High Impedance.
Logic High. The open circuit voltage is equal
to V OUT .
Logic Low.
High Impedance.
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