参数资料
型号: ADM693AN
厂商: Analog Devices Inc
文件页数: 12/16页
文件大小: 0K
描述: IC SUPER MPU 4.4 100MA WD 16DIP
标准包装: 25
类型: 备用电池电路
监视电压数目: 1
输出: 开路漏极,推挽式
复位: 高有效/低有效
复位超时: 最小为 35 ms
电压 - 阀值: 4.4V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 16-DIP(0.300",7.62mm)
供应商设备封装: 16-PDIP
包装: 管件
ADM690–ADM695
R =( V CC – 50 mV )/1 μ A
+5V
Note that the resistor will discharge the battery slightly. With a
V CC supply of 4.5 V, a suitable resistor is 4.3 M ? . With a 3 V
battery this will draw around 700 nA. This will be negligible in
most cases.
V BATT
R 1
R 2
PFI
V CC
V OUT
ADM690
ADM692
ADM694
RESET
0.1 μ F
μ P POWER
CMOS RAM
POWER
μ P SYSTEM
μ P RESET
BATTERY
R
ADM69x
BATTERY
+
V BATT
GND
PFO
WDI
μ P NMI
I/O LINE
Figure 22b. Preventing Spurious RESETS During Battery
Replacement
TYPICAL APPLICATIONS
ADM690, ADM692 AND ADM694
Figure 23 shows the ADM690/ADM692/ADM694 in a typical
power monitoring, battery backup application. V OUT powers the
CMOS RAM. Under normal operating conditions with V CC
Figure 23a. ADM690/ADM692/ADM694 Typical Application
Circuit A
Figure 23b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regu-
lator. This gives an earlier warning of an impending power fail-
ure. It is useful with processors operating at low speeds or
where there are a significant number of housekeeping tasks to be
completed before the power is lost.
present, V OUT is internally connected to V CC . If a power failure
occurs, V CC will decay and V OUT will be switched to V BATT
thereby maintaining power for the CMOS RAM. A RESET
INPUT
POWER
V > 8V
7805
+5V
0.1 μ F
pulse is also generated when V CC falls below 4.65 V for the
ADM690/ADM694 or 4.4 V for the ADM692. RESET will
remain low for 50 ms (200 ms for ADM694) after V CC returns
to 5 V.
The watchdog timer input (WDI) monitors an I/O line from the
μ P system. This line must be toggled once every 1.6 seconds to
R 1
R 2
PFI
V CC
V OUT
ADM690
ADM692
ADM694
RESET
0.1 μ F
μ P POWER
CMOS RAM
POWER
μ P SYSTEM
μ P RESET
verify correct software execution. Failure to toggle the line indi-
cates that the μ P system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
BATTERY
V BATT
GND
PFO
WDI
μ P NMI
I/O LINE
pulse is generated to initialize the processor.
If the watchdog timer is not needed, the WDI input should be
left floating.
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is com-
pared with a precision 1.3 V internal reference. If the input volt-
age drops below 1.3 V, a power fail output ( PFO ) signal is
generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage V T .
V T = (1.3 R 1 / R 2 ) + 1.3 V
R 1 / R 2 = ( V T /1.3) – 1
Figure 23b. ADM690/ADM692/ADM694 Typical Application
Circuit B
ADM691, ADM693, ADM695
A typical connection for the ADM691/ADM693/ADM695 is
shown in Figure 24. CMOS RAM is powered from V OUT . When
5 V power is present this is routed to V OUT . If V CC fails then
V BATT is routed to V OUT . V OUT can supply up to 100 mA from
V CC , but if more current is required, an external PNP transistor
can be added. When V CC is higher than V BATT , the BATT ON
output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1 μ F capacitor is connected to V OUT to
supply the transient currents for CMOS RAM. When V CC is
lower than V BATT , an internal 20 ? MOSFET connects the
backup battery to V OUT .
–12 –
REV. A
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