参数资料
型号: ADM708TANZ
厂商: Analog Devices Inc
文件页数: 10/16页
文件大小: 0K
描述: IC SUPERVISOR MPU 3.08V WD 8DIP
标准包装: 50
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,推挽式
复位: 高有效/低有效
复位超时: 最小为 160 ms
电压 - 阀值: 3.08V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
CIRCUIT INFORMATION
MANUAL RESET
WATCHDOG
INPUT (WDI)
MR
V CC
WATCHDOG
TRANSITION
DETECTOR
V CC
70 μ A
WATCHDOG
TIMER
RESET AND
WATCHDOG
TIMEBASE
RESET
GENERATOR
WATCHDOG
OUTPUT (WDO)
RESET,
(P = RESET)
The MR input allows other reset sources, such as a manual reset
switch, to generate a processor reset. The input is effectively
debounced by the timeout period (200 ms typical). The MR
input is TTL-/CMOS-compatible; it can also be driven by any
logic reset output. If unused, the MR input can be tied high or
left floating.
V REF *
ADM706P/ADM706R/
V CC
V RT
V RT
POWER-FAIL
INPUT (PFI)
1.25V
ADM706S/ADM706T
POWER-FAIL
OUTPUT (PFO)
RESET
t RS
t RS
* VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
Figure 13. ADM706 Functional Block Diagram
MR
MR EXTERNALLY
DRIVEN LOW
V CC
70 μ A
RESET
WDO
MR
V CC
POWER-FAIL
INPUT (PFI)
V REF *
1.25V
RESET
GENERATOR
ADM708R/ADM708S/
ADM708T
RESET
POWER-FAIL
OUTPUT (PFO)
NOTES
RESET = COMPLEMENT OF RESET
Figure 15. RESET, MR, and WDO Timing
WATCHDOG TIMER (ADM706x)
The watchdog timer circuit is used to monitor the activity of the
* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
Figure 14. ADM708 Functional Block Diagram
POWER-FAIL RESET
The reset output provides a reset (RESET or RESET) output
signal to the microprocessor whenever the V CC input is below
the reset threshold. The actual reset threshold voltage is dependent
on whether a P, R, S, or T suffix device is used. An internal timer
holds the reset output active for 200 ms after the voltage on V CC
rises above the threshold. This is intended as a power-on reset
signal for the microprocessor. It allows time for both the power
supply and the microprocessor to stabilize after power-up. If a
power supply brownout or interruption occurs, the reset line is
similarly activated and remains active for 200 ms after the supply
recovers. If another interruption occurs during an active reset
period, the reset timeout period continues for an additional 200 ms.
The reset output is guaranteed to remain valid with V CC as low
as 1 V. This ensures that the microprocessor is held in a stable
microprocessor to check that it is not stalled in an indefinite loop.
An output line on the processor is used to toggle the watchdog
input (WDI) line. If this line is not toggled within the timeout
period (1.6 seconds), the watchdog output (WDO) is driven low.
The WDO output is connected to a nonmaskable interrupt (NMI)
on the processor. Therefore, if the watchdog timer times out, an
interrupt is generated. The interrupt service routine is used to
rectify the problem.
The watchdog timer is cleared either by a high-to-low or by a
low-to-high transition on WDI. Pulses as narrow as 50 ns are
detected. The timer is also cleared by RESET/RESET going
active. Therefore, the watchdog timeout period begins after
reset goes inactive.
When V CC falls below the reset threshold, WDO is forced low
whether or not the watchdog timer has timed out. Normally,
this generates an interrupt, but it is overridden by RESET/RESET
going active.
shutdown condition as the power supply starts up.
t WP
t WD
t WD
t WD
The ADM706P provides an active high RESET signal; the
ADM706R/ADM706S/ADM706T provide an active low RESET
signal; and the ADM708R/ADM706S/ADM706T provide both
RESET and RESET.
WDI
WDO
RESET
RESET EXTERNALLY
TRIGGERED BY MR
t RS
Figure 16. Watchdog Timing
Rev. C | Page 10 of 16
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