参数资料
型号: ADMC328YN
厂商: Analog Devices, Inc.
英文描述: 28-Lead ROM-Based DSP Motor Controller with Current Sense
中文描述: 28 - ROM的铅基于DSP的电机控制器的电流检测
文件页数: 17/32页
文件大小: 234K
代理商: ADMC328YN
ADMC328
–17–
REV. B
Following reset,
V
C
= 0 at
t
= 0. This reset and the start of the
conversion process are initiated by the PWMSYNC pulse, as
shown in Figure 12. The width of the PWMSYNC pulse is
controlled by the PWMSYNCWT register and should be
programmed according to Figure 13 to ensure complete resetting.
In order to compensate for IC process manufacturing tolerances
(and to adjust for capacitor tolerances), the current source of the
ADMC328 is software programmable. The software setting of the
magnitude of the ICONST current generator is accomplished by
selecting one of eight steps over an approximately 20% cur-
rent range.
V1
PWMSYNC
V
VIL
COMPARATOR
OUTPUT
t
T
CRST
T
PWM
–T
CRST
t
VIL
V
C
V
CMAX
Figure 12. Analog Input Block Operation
The ADC system consists of four comparators and a single timer,
which may be clocked at either the DSP rate or half the DSP
rate depending on the setting of the ADCCNT bit (Bit 7) of the
MODECTRL register. When this bit is cleared, the timers count
at a slower rate of CLKIN. When this bit is set, they count at
CLKOUT or twice the rate of CLKIN. ADC1, ADC2, ADC3,
and ADCAUX are the registers that capture the conversion times,
which are effectively the timer value when the associated com-
parator trips.
CHARGING CAPACITOR – nF
200
0
0
10
D
100
150
50
2
4
6
8
Figure 13. PWMSYNCWT Program Value
ADC Resolution
The ADC is intrinsically linked to the PWM block through the
PWMSYNC pulse controlling the ADC conversion process.
Because of this link, the effective resolution of the ADC is a
function of both the PWM switching frequency and the rate at
which the ADC counter timer is clocked. For a CLKOUT period
of t
CK
and a PWM period of T
PWM
, the maximum count of the
ADC is given by:
Max Count
=
min
(4095, (
T
PWM
T
CRST
)/2
t
CK
)
for MODECTRL Bit
7 = 0
Max Count
=
min
(4095, (
T
PWM
T
CRST
)/
t
CK
)
for MODECTRL Bit
7 = 1
Where
T
PWM
is equal to the PWM period if operating in single
update mode, or it is equal to half that period if operating in
double update mode. For an assumed CLKOUT frequency of
20 MHz and PWMSYNC pulsewidth of 2.0
μ
s, the effective
resolution of the ADC block is tabulated for various PWM
switching frequencies in Table VII.
Table VII. ADC Resolution Examples
PWM
Freq.
(kHz)
MODECTRL[7] = 0
Max
Effective
Count
Resolution
MODECTRL[7] = 1
Max
Effective
Count
Resolution
2.4
4
8
18
25
4095
2480
1230
535
380
12
>11
>10
>9
>8
4095
4095
2460
1070
760
12
12
>11
>10
>9
Charging Capacitor Selection
The charging capacitor value is selected based on the sample
(PWM) frequency desired. A selected capacitor value that is
too small will reduce the available resolution of the ADC by
having the ramp voltage rise rapidly and convert too quickly,
not utilizing all possible counts available in the PWM cycle. Too
large a capacitor may not convert in the available PWM cycle,
returning 0xFFF. To select a charging capacitor use Figure 14,
select the sampling frequency desired, then determine if the cur-
rent source is to be tuned to a nominal 100
μ
A or left in the
default (0x0 code) trim state, then determine the proper charge
capacitor from the appropriate curve.
FREQUENCY – kHz
100
11
100
10
C
N
10
DEFAULT ICONST
TUNED ICONST
Figure 14. Timing Capacitor Selection
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