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参数资料
| 型号： | ADMC331-PB |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Single Chip DSP Motor Controller |
| 中文描述： | 单芯片DSP的电机控制器 |
| 文件页数： | 21/36页 |
| 文件大小： | 248K |
| 代理商： | ADMC331-PB |
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ADMC331
–21–
REV. B
AUX0
AUX1
AUX0
AUX1
2
(AUXTM1 + 1)
2
(AUXTM0 + 1)
2
AUXCH0
2
(AUXTM0 + 1)
2
AUXCH1
2
(AUXTM0 + 1)
2
(AUXTM1 + 1)
(A)
(B)
2
AUXCH1
2
AUXCH0
AUXCH1
Figure 13. Typical Auxiliary PWM Signals in (a) Independent
Mode and (b) Offset Mode (All Times in Increments of t
CK
)
Auxiliary PWM Interface, Registers and Pins
The registers of the auxiliary PWM system are summarized at
the end of the data sheet.
PWM DAC Equation
The PWM output can be filtered in order to produce a low
frequency analog signal between 0 V to 4.98 V dc. For example,
a 2-pole filter with a 1.2 kHz cutoff frequency will sufficiently
attenuate the PWM carrier. Figure 14 shows how the filter
would be applied.
C1
C2
R1
R2
R1 = R2 = 13k
C1 = C2 = 10nF
PWMDAC
Figure 14. Auxiliary PWM Output Filter
WATCHDOG TIMER
The ADMC331 incorporates a watchdog timer that can perform
a full reset of the DSP and motor control peripherals in the
event of software error. The watchdog timer is enabled by writ-
ing a timeout value to the 16-bit WDTIMER register. The
timeout value represents the number of CLKIN cycles required
for the watchdog timer to count down to zero. When the
watchdog timer reaches zero, a full DSP core and motor control
peripheral reset is performed. In addition, Bit 1 of the SYSSTAT
register is set so that after a watchdog reset the ADMC331 can
determine that the reset was due to the timeout of the watchdog
timer and not an external reset. Following a watchdog reset,
Bit 1 of the SYSSTAT register may be cleared by writing zero to
the WDTIMER register. This clears the status bit but does not
enable the watchdog timer.
On reset, the watchdog timer is disabled and is only enabled
when the first timeout value is written to the WDTIMER
register. To prevent the watchdog timer from timing out, the
user must write to the WDTIMER register at regular intervals
(shorter than the programmed WDTIMER period value). On all
but the first write to WDTIMER, the particular value written to
the register is unimportant since writing to WDTIMER simply
reloads the first value written to this register. The WDTIMER
register is memory mapped to data memory at location 0x2018.
PROGRAMMABLE DIGITAL INPUT/OUTPUT
The ADMC331 has 24 programmable digital I/O (PIO) pins:
PIO0
–
PIO23. Each pin can be individually configurable as
either an input or an output. Input pins can also be used to
generate interrupts. Each PIO pin includes an internal pull-
down resistor.
The PIO pins are configured as input or output by setting the
appropriate bits in the PIODIR0, PIODIR1 and PIODIR2
registers. The read/write registers PIODATA0, PIODATA1 and
PIODATA2 are used to set the state of an output pin or read the
state of an input pin. Writing to PIODATA0, PIODATA1 and
PIODATA2 affects only the pins configured as outputs. The
default state, after an ADMC331 reset, is that all PIOs are config-
ured as inputs.
Any pin can be configured as an independent edge-triggered
interrupt source. The pin must first be configured as an input
and then the appropriate bit must be set in the PIOINTEN0, or
PIOINTEN1 or PIOINTEN2 registers. A peripheral interrupt
is generated when the input level changes on any PIO pin con-
figured as an interrupt source. A PIO interrupt sets the appro-
priate bit in the PIOFLAG0, or PIOFLAG1 or PIOFLAG2
registers. The DSP peripheral interrupt service routine (ISR)
must read the PIOFLAG0, PIOFLAG1 and PIOFLAG2 regis-
ters to determine which PIO pin was the source of the PIO
interrupt. Reading the PIOFLAG0, PIOFLAG1 and PIOFLAG2
registers will clear them.
PIO Registers
The configuration of all registers of the PIO system is shown at
the end of the data sheet.
INTERRUPT CONTROL
The ADMC331 can respond to 34 different interrupt sources
with minimal overhead. Eight of these interrupts are internal
DSP core interrupts and twenty six are from the Motor Control
Peripherals. The eight DSP core interrupts are SPORT0 re-
ceive and transmit, SPORT1 receive (or
IRQ0
) and transmit (or
IRQ1
), the internal timer and two software interrupts. The
Motor Control interrupts are the 24 peripheral I/Os and two
from the PWM (PWMSYNC pulse and PWMTRIP). All mo-
tor control interrupts are multiplexed into the DSP core via the
peripheral
IRQ2
interrupt. They are also internally prioritized
and individually maskable. The start address in the interrupt
vector table for the ADMC331 interrupt sources is shown in
Table VIII. The interrupts are listed from high priority to the
lowest priority.
The PWMSYNC interrupt is triggered by a low-to-high transi-
tion on the PWMSYNC pulse. The
PWMTRIP
interrupt is
triggered on a high-to-low transition on the
PWMTRIP
pin. A
PIO interrupt is detected on any change of state (high-to-low or
low-to-high) on the PIO lines.
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