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参数资料
| 型号： | ADMC331-PB |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Single Chip DSP Motor Controller |
| 中文描述： | 单芯片DSP的电机控制器 |
| 文件页数： | 3/36页 |
| 文件大小： | 248K |
| 代理商： | ADMC331-PB |
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ADMC331
–3–
REV. B
TIMING PARAMETERS
Parameter
Min
Max
Unit
Clock Signals
t
CK
is defined as 0.5 t
CKI
. The ADMC331 uses an input clock with a frequency equal
to half the instruction rate; a 13 MHz input clock (which is equivalent to 76.9 ns)
yields a 38.5 ns processor cycle (equivalent to 26 MHz). t
CK
values within the range
of 0.5 t
CKI
period should be substituted for all relevant timing parameters to obtain
specification value.
Example: t
CKH
= 0.5 t
CK
– 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.
Timing Requirements
:
t
CKI
CLKIN Period
t
CKIL
CLKIN Width Low
t
CKIH
CLKIN Width High
Switching Characteristics
:
t
CKL
CLKOUT Width Low
t
CKH
CLKOUT Width High
t
CKOH
CLKIN High to CLKOUT High
Control Signals
Timing Requirement:
t
RSP
RESET Width Low
PWM Shutdown Signals
Timing Requirement:
t
PWMTPW
PWMTRIP
Width Low
76.9
20
20
150
ns
ns
ns
0.5 t
CK
– 10
0.5 t
CK
– 10
0
ns
ns
ns
20
5 t
CK1
ns
2 t
CK
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
t
CKOH
t
CKH
t
CKI
t
CKIH
t
CKL
t
CKIL
Figure 1. Clock Signals
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