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参数资料
| 型号： | ADMC331BST |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | Single Chip DSP Motor Controller |
| 中文描述： | 0-BIT, 16.384 MHz, OTHER DSP, PQFP80 |
| 封装： | PLASTIC, TQFP-80 |
| 文件页数： | 13/36页 |
| 文件大小： | 248K |
| 代理商： | ADMC331BST |
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ADMC331
–13–
REV. B
The PWM generator of the ADMC331 also provides an output
pulse on the PWMSYNC pin that is synchronized to the PWM
switching frequency. In single update mode, a PWMSYNC
pulse is produced at the start of each PWM period. In double
update mode, an additional PWMSYNC pulse is produced at
the midpoint of each PWM period. The width of the PWM-
SYNC pulse is programmable through the PWMSYNCWT
register.
The PWM signals produced by the ADMC331 can be shut-off
in two different ways. Firstly there is a dedicated asynchronous
PWM shutdown pin,
PWMTRIP
, that when brought LO, in-
stantaneously places all six PWM outputs in the OFF state (as
determined by the state of the PWMPOL pin). This hardware
shutdown mechanism is asynchronous so that the associated
PWM disable circuitry does not go through any clocked logic,
thereby ensuring correct PWM shutdown even in the event of a
loss of DSP clock. In addition to the hardware shutdown fea-
ture, the PWM system may be shutdown in software by writing
to the PWMSWT register.
Status information about the PWM system of the ADMC331 is
available to the user in the SYSSTAT register. In particular,
the state of the
PWMTRIP
, PWMPOL and
PWMSR
pins is
available, as well as a status bit that indicates whether operation
is in the first half or the second half of the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 5. The generation of the six output PWM signals on
pins AH to CL is controlled by four important blocks:
The Three-Phase PWM Timing Unit, which is the core of the
PWM controller, generates three pairs of complemented and
dead time adjusted center based PWM signals.
The Switched Reluctance Control Unit transforms the three-
phase outputs into six PWM wave forms for switched reluc-
tance gate drive signals.
The Output Control Unit allows the redirection of the out-
puts of the Three-Phase Timing Unit for each channel to
either the high side or the low side output. In addition, the
Output Control Unit allows individual enabling/disabling of
each of the six PWM output signals.
The GATE Drive Unit provides the correct polarity output
PWM signals based on the state of the PWMPOL pin. The
Gate Drive Unit also permits the generation of the high fre-
quency chopping frequency and its subsequent mixing with
the PWM signals.
The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, CLKOUT, and is capable of gener-
ating two interrupts to the DSP core. One interrupt is gener-
ated on the occurrence of a PWMSYNC pulse and the other is
generated on the occurrence of any PWM shutdown action.
Three-Phase Timing Unit
The 16-bit three-phase timing unit is the core of the PWM
controller and produces three pair of pulsewidth modulated
signals with high resolution and minimal processor overhead.
The outputs of this timing unit are active LO such that a low
level is interpreted as a command to turn ON the associated
power device. There are four main configuration registers
(PWMTM, PWMDT, PWMPD and PWMSYNCWT) that
determine the fundamental characteristics of the PWM outputs.
In addition, the operating mode of the PWM (single or double
update mode) is selected by Bit 6 of the MODECTRL register.
PWMTM (15 . . . 0)
PWMDT (9 . . . 0)
PWMPD (9 . . . 0)
PWMSYNCWT (7 . . . 0)
MODECTRL (6)
PWMSEG
PWMGATE
OUTPUT
CONTROL
UNIT
SYNC
GATE
DRIVE
UNIT
CLK
AH
AL
BH
BL
CH
CL
CLKOUT
PWMTRIP
PWMSYNC
SWITCHED
RELUCTANCE
CONTROL
UNIT
SR
PWM DUTY CYCLE
REGISTERS
PWM CONFIGURATION
REGISTERS
POL
PWMPOL
PWMTRIP
TO INTERRUPT
CONTROLLER
OR
THREE-PHASE
PWM TIMING
UNIT
CLK
RESET
SYNC
PWMSR
PWMSWT (0)
PWMCHA (15 . . . 0)
PWMCHB (15 . . . 0)
PWMCHC (15 . . . 0)
PWMSYNC
Figure 5. Overview of the PWM Controller of the ADMC331
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