参数资料
型号: ADMC331BST
厂商: ANALOG DEVICES INC
元件分类: 数字信号处理
英文描述: Single Chip DSP Motor Controller
中文描述: 0-BIT, 16.384 MHz, OTHER DSP, PQFP80
封装: PLASTIC, TQFP-80
文件页数: 26/36页
文件大小: 248K
代理商: ADMC331BST
ADMC331
–26–
REV. B
System Controller Registers
The system controller includes three registers, MODECTRL,
SYSSTAT and IRQFLAG registers. The format of these regis-
ters is shown at the end of the data sheet.
The MODECTRL register controls different multiplexing,
PWM interrupt and operating modes:
Bit 0 and 1 control the multiplexing of the ADC auxiliary
channels.
Bit 2 enables/disables the
PWMTRIP
interrupt: if the bit is
set the interrupt is enabled.
Bit 3 enables/disables the PWMSYNC interrupt: if the bit is
set the interrupt is enabled.
Bit 4 controls the multiplexing of the SPORT1 pins: if the bit
is set DR1B is selected.
Bit 5 controls the configuration of SPORT1 as a UART inter-
face: if the bit is set UART mode is enabled.
Bit 6 selected the PWM operating mode: single or double
duty cycle update modes. If the bit is set double update mode
is selected.
Bit 7 selects the ADC counter frequency: if the bit is set full
DSP clkout frequency is selected.
Bit 8 selects the Auxiliary PWM operating mode: offset or
independent modes: if the bit is set independent mode is
selected.
The SYSSTAT register displays various status information:
Bit 0 indicates the status of the
PWMTRIP
pin: if this bit is
high, then
PWMTRIP
pin is high and no PWMTRIP is oc-
curring, if this bit is low, then the PWM is currently shut
down.
Bit 1 indicates the status of the watchdog flag register: this bit
is set following a watchdog timeout.
Bit 2 indicates the status of the PWMPOL pin: if this bit is
set, the PWMPOL pin is high and active high PWM outputs
will be produced.
Bit 3 indicates the status of the PWM timer.
Bit 4 indicates the status of the
PWMSR
pin: if this bit is set
to a logic one, the
PWMSR
pin is low and switched reluc-
tance mode is enabled.
The IRQFLAG register indicates the occurrence of PWM
interrupts:
Bit 0 indicates that a
PWMTRIP
interrupt, either hardware of
software, has occurred.
Bit 1 indicates that a PWMSYNC interrupt has occurred.
Register Memory Map
The address, name, used bits and function of all motor control
peripheral registers of the ADMC331 are tabulated in Table X.
In addition, the relevant DSP core registers are tabulated in
Table XI. Full details of the DSP core registers can be obtained
by referring to the ADSP-2171 sections of the
ADSP-2100 Family
User
s Manual, Third Edition.
Development Kit
To facilitate device evaluation and programming, an evaluation
kit (ADMC331-EVAL KIT) is available from Analog Devices.
The evaluation kit consists of an evaluation board and the
Motion Control Debugger software. The evaluation kit con-
tains latest programming and device information. It is recom-
mended that the evaluation kit be used for initial program
development.
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