参数资料
型号: ADMC401BST
厂商: ANALOG DEVICES INC
元件分类: 数字信号处理
英文描述: Single-Chip, DSP-Based High Performance Motor Controller
中文描述: 24-BIT, 13 MHz, OTHER DSP, PQFP144
封装: PLASTIC, LQFP-144
文件页数: 7/60页
文件大小: 417K
代理商: ADMC401BST
ADMC401
–7–
REV. B
Parameter
Bus Request/Grant
Timing Requirements
:
t
BH
t
BS
Switching Characteristics
:
t
SD
Min
Max
Unit
BR
Hold after CLKOUT High
1
BR
Setup before CLKOUT Low
1
0.25t
CK
+2
0.25t
CK
+ 17
ns
ns
CLKOUT High to
DMS
,
PMS
,
BMS
,
RD
,
WR
Disable
DMS
,
PMS
,
BMS
,
RD
,
WR
Disable to
BG
Low
BG
High to
DMS
,
PMS
,
BMS
,
RD
,
WR
Enable
DMS
,
PMS
,
BMS
,
RD
,
WR
Enable to CLKOUT High
DMS
,
PMS
,
BMS
,
RD
,
WR
Disable to
BGH
Low
2
BGH
High to
DMS
,
PMS
,
BMS
,
RD
,
WR
Enable
2
0.25t
CK
+ 10
ns
t
SDB
0
ns
t
SE
0
ns
t
SEC
0.25t
CK
– 7
ns
t
SDBH
0
ns
t
SEH
0
ns
NOTES
1
BR
is an asynchronous signal. If
BR
meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the
ADSP-2100 Family User’s Manual,
Third Edition for
BR
/
BG
cycle relationships.
2
BGH
is asserted when the bus is granted and the processor requires control of the bus to continue.
BR
CLKOUT
PMS
,
DMS
BMS
,
RD
WR
BG
CLKOUT
BGH
t
BH
t
BS
t
SD
t
SDB
t
SDBH
t
SEH
t
SE
t
SEC
Figure 3. Bus Request–Bus Grant
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