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参数资料
| 型号： | ADN2804ACPZ-500RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/24页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA REC 622MBPS 32-LFCSP |
| 标准包装： | 500 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | CML |
| 输出： | LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
ADN2804
Data Sheet
Rev. C | Page 20 of 24
3. Read back MISC[2]. If it is 0, the measurement is not
complete. If it is 1, the measurement is complete and the
data rate can be read back on FREQ[22:0]. The time for a
data rate measurement is typically 80 ms.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2804 compares the frequency of
the incoming data to the incoming reference clock and returns a
ratio of the two frequencies to within 0.01% (100 ppm) accuracy.
The accuracy error of the reference clock is added to the accuracy
of the ADN2804 data rate measurement. For example, if a 100 ppm
accuracy reference clock is used, the total accuracy of the measure-
ment is within 200 ppm.
4. Read back the data rate from FREQ2[6:0], FREQ1[7:0], and
FREQ0[7:0].
The data rate can be determined by
[]
(
)
_
14
(
2
/
0
.
22
RATE
SEL
REFCLK
DATARATE
f
FREQ
f
+
×
=
where:
FREQ[22:0] is the reading from FREQ2[6:0] (MSB byte,
FREQ1[7:0], and FREQ0[7:0] (LSB byte).
fDATARATE is the data rate (Mbps).
fREFCLK is the REFCLK frequency (MHz).
SEL_RATE is the setting from CTRLA[7, 6].
The reference clock can range from 10 MHz to 160 MHz.
By default, the ADN2804 expects a reference clock between
10 MHz and 20 MHz. If the reference clock is between 20 MHz
and 40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz,
the user must configure the ADN2804 for the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7, 6]. Using the reference clock to determine the frequency
of the incoming data does not affect the manner in which the
part locks onto data. In this mode, the reference clock is used
only to determine the frequency of the data.
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, because the reference frequency falls into the
20 MHz to 40 MHz range, setting CTRLA[7, 6] to [01],.
Assume for this example that the input data rate is 622.08 Mb/s
(OC12). After following Step 1 through Step 4, the value that is
read back on FREQ[22:0] = 0x9B851, which is equal to 637 × 103.
Plugging this value into the equation yields
Prior to reading back the data rate using the reference clock, the
CTRLA[7, 6] bits must be set to the appropriate frequency
range with respect to the reference clock being used. A fine data
rate readback is then executed as follows:
637e3 × 32e6/2(14 + 1) = 622.08 Mbps
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Step 2 through Step 4 to read back the new data rate.
1. Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2804. This bit is level
sensitive and can perform subsequent frequency measurements
without being reset.
2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].
This initiates a new data rate measurement.
Note that a data rate readback is valid only if LOL is low. If LOL
is high, the data rate readback is invalid.
Table 12.
D22
D21 ... D17
D16
D15
D14 ... D9
D8
D7
D6 ... D1
D0
FREQ2[6:0]
FREQ1[7:0]
FREQ0[7:0]
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相关代理商/技术参数 |
参数描述 |
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| ADN2804ACPZ-RL7 | 功能描述:IC CLK/DATA REC 622MBPS 32-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ADN2805 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.25 Gbps Clock and Data Recovery IC |
| ADN2805ACPZ | 功能描述:IC CLK/DATA REC 1.25GBPS 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
| ADN2805ACPZ-500RL7 | 功能描述:IC CLK/DATA REC 1.25GBPS 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
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