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| 型号： | ADN2806ACPZ-500RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA REC 622MBPS 32-LFCSP |
| 标准包装： | 500 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | CML |
| 输出： | LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
ADN2806
Rev. C | Page 17 of 20
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using plugged vias so that solder does not leak
through the vias during reflow.
Use of a 22 μF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they
should be placed between ADN2806 supply pins VCC and VEE,
as close as possible to the ADN2806 VCC pins.
If connections to the supply and ground are made through
vias, the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/
DATAOUTN output buffers. Refer to Figure 19 for the
recommended connections.
By placing the power supply and GND planes adjacent to each
other and using close spacing between the planes, excellent high
frequency decoupling can be realized. The capacitance is given by
pF
/
0.88ε
r
d
A
C
PLANE
where:
r
is the dielectric constant of the PCB material.
A
is the area of the overlap of power and GND planes (cm2).
d
is the separation between planes (mm).
For FR-4, r = 4.4 and d = 0.25 mm; therefore,
CPLANE
~ 15 pF/cm2.
50 TRANSMISSION LINES
DATAOUTP
DATAOUTN
CLKOUTP
CLKOUTN
0.1F
22F
1nF
0.1F
1.6F
0.1F
0.47F ±20%
>300M INSULATION RESISTANCE
1nF
0.1F
1nF
+
VCC
50
LIM
VCC
NC
C
I2C CONTROLLER
VCC
1
TEST1
2
VCC
3
VREF
4
NIN
5
PIN
6
NC
7
NC
8
VEE
24
VCC
23
VEE
22
NC
21
SDA
20
SCK
19
SADDR5
18
VCC
17
VEE
9
N
C
10
R
E
F
C
L
K
P
11
R
E
F
C
L
K
N
12
V
C
13
V
E
14
C
F
2
15
C
F
1
16
L
O
L
32
T
E
S
T
2
31
V
C
30
V
E
29
D
A
T
A
O
U
T
P
28
D
A
T
A
O
U
T
N
27
S
Q
U
E
L
C
H
26
C
L
K
O
U
T
P
25
C
L
K
O
U
T
N
EXPOSED PAD
TIED OFF TO
VEE PLANE
WITH VIAS
0
5831-
03
1
Figure 19. Typical ADN2806 Applications Circuit
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参数描述 |
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| ADN2806ACPZ-RL7 | 功能描述:IC CLK/DATA REC 622MBPS 32-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ADN2807 | 制造商:AD 制造商全称:Analog Devices 功能描述:155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2807ACP | 制造商:Analog Devices 功能描述:CDR 155.52Mbps/166.63Mbps/622.08Mbps/666.51Mbps SONET/SDH 48-Pin LFCSP EP Tray |
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