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| 型号： | ADN4600ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/28页 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SWITCH 8X8 64LFCSP |
| 标准包装： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉点开关 |
| 电路： | 1 x 8:8 |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 1.7 V ~ 3.6 V |
| 电流 - 电源： | 460mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 标准包装 |
| 其它名称： | ADN4600ACPZ-R7DKR |
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Data Sheet
ADN4600
Rev. A | Page 13 of 28
THEORY OF OPERATION
INTRODUCTION
The ADN4600 is an 8 × 8, buffered, asynchronous, 8-channel
crosspoint switch that allows fully nonblocking connectivity
between its transmitters and receivers. The switch supports
multicast and broadcast operation, allowing the ADN4600 to
work in redundancy and port-replication applications.
RECEIVE
EQUALIZATION
CROSSPOINT
ARRAY
TRANSMIT
PRE-EMPHASIS
CONTROL LOGIC
ADN4600
IP[7:0]
IN[7:0]
ADDR[1:0]
SCL
SDA
RESETB
OP[7:0]
ON[7:0]
07061-
003
EQ
PE
Figure 27. Simplified Functional Block Diagram
The ADN4600 offers extensively programmable output levels
and pre-emphasis, as well as a squelch function and the ability
to fully disable the device. The receivers integrate a programmable,
multizero transfer function that has been optimized to compensate
either typical backplane or typical cable losses. The ADN4600
provides a balanced, high speed switch core that maintains low
channel-to-channel skew and preserves edge rates.
The I/O on-chip termination resistors are tied to user-settable
supplies to support dc coupling in various logic styles. The
ADN4600 supports a wide core supply range; VCC can be set
from 1.8 V to 3.3 V. These features together with programmable
transmitter output levels allow for several dc- and ac-coupled
I/O configurations.
RECEIVERS
Input Structure and Input Levels
VCC
VTTI
IPx
INx
VEE
SIMPLIFIED RECEIVER INPUT CIRCUIT
RLN
RL
RLP
RL
Q1
Q2
I1
R3
1k
R1
750
R2
750
RN
52
RP
52
07061-
004
Figure 28. Simplified Input Structure
The ADN4600 receiver inputs incorporate 50 Ω termination
resistors, ESD protection, and a multizero transfer function
equalizer that can be optimized for backplane and cable operation.
Each receive channel also provides a positive/negative (P/N)
inversion function, which allows the user to swap the sign of the
input signal path to eliminate the need for board-level
crossovers in the receiver channel.
Table 5 illustrates some, but not all, possible combinations of
input supply voltages.
Equalization Settings
The ADN4600 receiver incorporates a multizero transfer
function with a continuous time equalizer, providing up to
22 dB of high-frequency boost at 2.25 GHz to compensate for
up to 30 in. of FR4 at 4.25 Gbps. The ADN4600 also allows
independent control of the equalizer transfer function on each
channel through the I2C control interface.
In the basic mode of operation, the equalizer transfer function
allows independent control of the boost in two frequency ranges
for optimal matching with the loss shape of the channel (for
example, the shape due primarily to skin effect or to dielectric
loss). The total equalizer shape space is reduced to two independent
frequency response groups—one optimized for cable and the
other optimized for FR4 material. The RX EQ bits of the
RX[7:0] configuration registers provide eight settings for each
frequency response group to ease programming for typical
channels.
Table 6 summarizes the high-frequency boost for the frequency
response grouping optimized for the FR4 material; it lists the basic
control settings and the typical length of FR4 trace compensated
for by each setting. All eight channels of the ADN4600 use the
FR4-optimized frequency response grouping by default. The
user can override this default by setting the respective RX LUT
select bit high and then selecting the frequency response grouping
by setting the RX LUT FR4/CX4 bit high for FR4 and low for
cable. Setting the RX EQBY bit of the RX[7:0] configuration
registers high sets the equalization to 1.5 dB of boost, which
compensates for 0 m to 2 m of CX4 or 0 in. to 10 in. of FR4.
In the advanced mode of operation, full control of the equalizer is
available through the I2C control interface. The user can specify
the boost in the midfrequency range and the boost in the high
frequency range independently. This is accomplished by
circumventing the frequency response groupings shown in
Table 6 by setting the EQ CTL SRC bit (Bit 6 of the RX[7:0]
EQ1 control registers) high and writing directly to the equalizer
control bits on a per channel basis. Therefore, write values to
Bits[5:0] of the RX[7:0] EQ1 control registers and to Bits[5:0]
of the RX[7:0] EQ3 control registers for the channel of interest.
The bits of these registers are ordered such that Bit 5 is a sign
bit, and midlevel boost is centered around 0x00. Setting Bit 5
low and increasing the LSBs decreases the boost, whereas
setting Bit 5 high and increasing the LSBs increases the boost.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADN4600-EVALZ | 制造商:Analog Devices 功能描述:Development Kit For ADN4600 4.25 Gbps, 8 X 8, Asynchronous Nchronous Crosspoint Switch 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) |
| ADN4600XCPZ | 制造商:Analog Devices 功能描述:4.25GBPS 8X8 DIGITAL CROSSPOINT 64-PIN LFCSP - Rail/Tube |
| ADN4604 | 制造商:AD 制造商全称:Analog Devices 功能描述:4.25 Gbps, 16 × 16, Digital Crosspoint Switch |
| ADN4604ASVZ | 功能描述:IC CROSSPOINT SWIT 16X16 100TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 模拟开关，多路复用器，多路分解器 系列:XStream™ 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 功能:开关 电路:单刀单掷 导通状态电阻:48 欧姆 电压电源:单电源 电压 - 电源，单路/双路(±):2.7 V ~ 5.5 V 电流 - 电源:5µA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:托盘 |
| ADN4604ASVZ-RL | 功能描述:IC CROSSPOINT SWIT 16X16 100TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 模拟开关，多路复用器，多路分解器 系列:XStream™ 其它有关文件:STG4159 View All Specifications 标准包装:5,000 系列:- 功能:开关 电路:1 x SPDT 导通状态电阻:300 毫欧 电压电源:双电源 电压 - 电源，单路/双路(±):±1.65 V ~ 4.8 V 电流 - 电源:50nA 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:7-WFBGA，FCBGA 供应商设备封装:7-覆晶 包装:带卷 (TR) |
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