参数资料
| 型号： | ADN4670BSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 1/12页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:10 32LQFP |
| 标准包装： | 1 |
| 类型： | 扇出缓冲器（分配），多路复用器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:10 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | LVDS |
| 输出： | LVDS |
| 频率 - 最大： | 1.1GHz |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 托盘 |
Programmable Low Voltage
1:10 LVDS Clock Driver
Data Sheet
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2010–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Low output skew <30 ps (typical)
Distributes one differential clock input to 10 LVDS clock
outputs
Programmable—one of two differential clock inputs can be
selected (CLK0, CLK1) and individual differential clock
outputs enabled/disabled
Signaling rate up to 1.1 GHz (typical)
2.375 V to 2.625 V power supply range
±100 mV differential input threshold
Input common-mode range from rail-to-rail
I/O pins fail-safe during power-down: VDD = 0 V
Available in 32-lead LFCSP and LQFP packages
Industrial operating temperature range: 40°C to +85°C
APPLICATIONS
Clock distribution networks
FUNCTIONAL BLOCK DIAGRAM
9 8 7 6 5 4 3 2 1 0
10
12-BIT
COUNTER
11-BIT SHIFT REGISTER
11-BIT CONTROL REGISTER
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CK
SI
EN
CLK0
CLK1
MUX
1
0
CLK0
CLK1
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
0
1
08870-
001
Figure 1.
GENERAL DESCRIPTION
The ADN4670 is a low voltage differential signaling (LVDS)
clock driver that expands a differential clock input signal to
10 differential clock outputs. The device is programmable
using a simple serial interface, so that one of two clock inputs
can be selected (CLK0/CLK0 or CLK1/CLK1) and any of the
differential outputs (Q0/Q0 to Q9/Q9) can be enabled or
disabled (tristated). The ADN4670 is designed for use in 50
transmission line environments.
When the enable input EN is high, the device may be pro-
grammed by clocking 11 data bits into the shift register. The
first 10 bits determine which outputs are enabled (0 = disabled,
1 = enabled), while the 11th bit selects the clock input (0 =
CLK0, 1 = CLK1). A 12th clock pulse transfers data from the
shift register to the control register.
The ADN4670 is fully specified over the industrial temperature
range and is available in a 32-lead LFCSP and LQFP packages.
相关PDF资料 |
PDF描述 |
|---|---|
| ADS7864YB/250G4 | IC 12BIT 500KHZ 6CH ADC 48-TQFP |
| ADS7883SBDBVR | IC ADC 12-BIT 3MSPS SOT23-6 |
| ADS8361IDBQG4 | IC ADC DUAL 16BIT 500KSPS 24QSOP |
| ADS8364Y/250G4 | IC ADC LP 16BIT 250KSPS 64-TQFP |
| ADS8412IPFBRG4 | IC ADC 16BIT 2MSPS 48-TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADN4670BSTZ-REEL7 | 功能描述:IC CLOCK BUFFER MUX 2:10 32LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:- 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ADN4690E | 制造商:AD 制造商全称:Analog Devices 功能描述:3.3 V, 100 Mbps, Half- and Full-Duplex |
| ADN4690EBRZ | 功能描述:IC INTERFACE TXRX RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:* 标准包装:98 系列:* |
| ADN4690EBRZ-RL7 | 功能描述:IC TXRX MLVDS 100MBPS 8SOIC RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:* 标准包装:121 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:3 V ~ 3.6 V 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-DFN（3x3） 包装:管件 |
| ADN4691E | 制造商:AD 制造商全称:Analog Devices 功能描述:3.3 V, 100 Mbps, Half- and Full-Duplex |
发布紧急采购，3分钟左右您将得到回复。