参数资料
型号: ADN4692EBRZ
厂商: Analog Devices Inc
文件页数: 7/20页
文件大小: 0K
描述: IC INTERFACE TXRX
标准包装: 56
系列: *
Data Sheet
ADN4690E/ADN4692E
Rev. 0 | Page 15 of 20
GLITCH-FREE POWER-UP/POWER-DOWN
To minimize disruption to the bus when adding nodes, the
M-LVDS outputs of the device are kept glitch-free when when
the device is powering up or down. This feature allows insertion
of devices onto a live M-LVDS bus because the bus outputs are
not switched on before the device is fully powered. In addition,
all outputs are placed in a high impedance state when the device is
powered off.
FAULT CONDITIONS
The ADN4690E/ADN4692E contain short-circuit current
protection that protects the part under fault conditions in the
case of short circuits on the bus. This protection limits the current
in a fault condition to 24 mA at the transmitter outputs for
short-circuit faults between 1 V and +3.4 V. Any network fault
must be cleared to avoid data transmission errors and to ensure
reliable operation of the data network and any devices that are
connected to the network.
RECEIVER INPUT THRESHOLDS/FAIL-SAFE
The Type 1 receivers of the ADN4690E/ADN4692E incorporate
25 mV of hysteresis. This ensures that slow-changing signals or
a loss of input does not result in oscillation of the receiver output.
Type 1 receiver thresholds are ±50 mV, so the state of the receiver
output is indeterminate if the differential between A and B is
about 0 V. This state occurs if the bus is idle (approximately 0 V on
both A and B) with no drivers enabled on the attached nodes.
The different receiver thresholds are illustrated in Figure 35.
See Table 11 for receiver output states under various conditions.
TYPE 1 RECEIVER
OUTPUT
LOGIC 1
LOGIC 0
D
IFF
E
R
E
N
TI
A
L
I
N
PUT
VO
LT
AG
E
(
V
IA
V
IB
)(
V
)
0.25
0.15
0.05
–0.05
–0.15
0
10
47
1-03
4
UNDEFINED
Figure 35. Input Threshold Voltages
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