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参数资料
| 型号： | ADP121-3.0-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADP121 3V |
| 设计资源： | Low power, Long Range, ISM Wireless Measuring Node (CN0164) |
| 标准包装： | 1 |
| 每 IC 通道数： | 1 - 单 |
| 输出电压： | 3V |
| 电流 - 输出： | 150mA |
| 输入电压： | 2.3 ~ 5.5 V |
| 稳压器类型： | 正，固定式 |
| 工作温度： | -40°C ~ 125°C |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP121 |
| 产品目录页面： | 792 (CN2011-ZH PDF) |
| 相关产品： | ADP121-ACBZ30R7TR-ND - IC REG LDO 3V .15A 4WLCSP ADP121-AUJZ30R7DKR-ND - IC REG LDO 3V .15A TSOT-23-5 |
Data Sheet
ABSOLUTE MAXIMUM RATINGS
ADP121
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
?0.3 V to +6.5 V
?0.3 V to VIN
?0.3 V to +6.5 V
?65°C to +150°C
?40°C to +125°C
JEDEC J-STD-020
Junction-to-ambient thermal resistance, θ JA , is based on
modeling and calculation using a four-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ JA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θ JA are based on a 4-layer, 4” × 3”, circuit
board. Refer to JESD 51-7 and JESD 51-9 for detailed
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP121 can be damaged when the junction
temperature limits are exceeded. Monitoring the ambient
temperature does not guarantee that the junction temperature
(T J ) is within the specified temperature limits. In applications
with high power dissipation and poor thermal resistance, the
maximum ambient temperature may have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. T J of the device is dependent on
the ambient temperature (T A ), the power dissipation of the
device (P D ), and the junction-to-ambient thermal resistance of
the package (θ JA ). T J is calculated from T A and P D using the
following formula:
information on the board construction. For additional
information, see AN-617 Application Note, MicroCSP TM
Wafer Level Chip Scale Package .
Ψ JB is the junction-to-board thermal characterization parameter
measured in °C/W. Ψ JB is based on modeling and calculation
using a four-layer board. The JESD51-12 Guidelines for Reporting
and Using Package Thermal Information states that thermal
characterization parameters are not the same as thermal
resistances. Ψ JB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θ JB . Therefore, Ψ JB thermal paths include
convection from the top of the package as well as radiation
from the package, factors that make Ψ JB more useful in real-
world applications. Maximum T J is calculated from the board
temperature (T B ) and P D using the following formula:
T J = T B + ( P D × Ψ JB )
Refer to JESD51-8 and JESD51-12 for more detailed
information about Ψ JB .
THERMAL RESISTANCE
θ JA and Ψ JB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
T J = T A + ( P D × θ JA )
Package Type
5-Lead TSOT
4-Ball 0.4 mm Pitch WLCSP
θ JA
170
260
Ψ JB
43
58
Unit
°C/W
°C/W
ESD CAUTION
Rev. G | Page 5 of 20
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