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| 型号： | ADP124ARHZ-2.85-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 2.85V .5A 8MSOP |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 2.85V |
| 输入电压： | 最高 5.5V |
| 电压 - 压降（标准）： | 0.13V @ 500mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 500mA（最小值） |
| 电流 - 限制（最小）： | 550mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 8-MSOP-EP |
| 包装： | 标准包装 |
| 产品目录页面： | 792 (CN2011-ZH PDF) |
| 其它名称： | ADP124ARHZ-2.85-R7DKR |
Data Sheet
THEORY OF OPERATION
The ADP124/ADP125 are low quiescent current, low dropout
linear regulators that operate from 2.3 V to 5.5 V and can provide
up to 500 mA of output current. Drawing a low 210 μA of quies-
cent current (typical) at full load makes the ADP124/ADP125
ADP124/ADP125
The ADP124/ADP125 use the EN pin to enable and disable the
VOUT pin under normal operating conditions. When EN is high,
VOUT turns on; when EN is low, VOUT turns off. For automatic
startup, EN can be tied to VIN.
ideal for battery-operated portable equipment. Shutdown current
consumption is typically 100 nA.
Optimized for use with small 1 μF ceramic capacitors, the
ADP124/ADP125 provide excellent transient performance.
Internally, the ADP124/ADP125 consist of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass transistor.
VIN
GND
ADP124
SHORT CIRCUIT,
UVLO, AND
THERMAL
PROTECT
R1
VOUT
VOUT SENSE
Output current is delivered via the PMOS pass device, which is
controlled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
EN
SHUTDOWN
0.5V REFERENCE
R2
and amplifies the difference. If the feedback voltage is lower than
the reference voltage, the gate of the PMOS device is pulled lower,
allowing more current to pass and increasing the output voltage.
If the feedback voltage is higher than the reference voltage, the
gate of the PMOS device is pulled higher, allowing less current
to pass and decreasing the output voltage.
NOTES
1. R1 AND R2 ARE INTERNAL RESISTORS, AVAILABLE ON
THE ADP124 ONLY.
Figure 28. ADP124 Internal Block Diagram (Fixed Output)
The adjustable ADP125 has an output voltage range of 0.8 V to
5.0 V. The output voltage is set by the ratio of two external resistors,
VIN
ADP125
VOUT
as shown in Figure 2. The device servos the output to maintain
the voltage at the ADJ pin at 0.5 V referenced to ground. The
current in R1 is then equal to 0.5 V/R2 and the current in R1 is
the current in R2 plus the ADJ pin bias current. The ADJ pin
bias current, 15 nA at 25°C, flows through R1 into the ADJ pin.
GND
SHORT CIRCUIT,
UVLO, AND
THERMAL
PROTECT
The output voltage can be calculated using the equation:
V OUT = 0.5 V(1 + R1 / R2 ) + ( ADJ I-BIAS )( R1 )
EN
SHUTDOWN
0.5V REFERENCE
ADJ
The value of R1 should be less than 200 kΩ to minimize errors
in the output voltage caused by the ADJ pin bias current. For
example, when R1 and R2 each equal 200 kΩ, the output voltage
is 1.0 V. The output voltage error introduced by the ADJ pin
bias current is 3 mV or 0.3%, assuming a typical ADJ pin bias
current of 15 nA at 25°C.
Note that in shutdown, the output is turned off and the divider
current is 0.
Rev. C | Page 11 of 20
Figure 29. ADP125 Internal Block Diagram (Adjustable Output)
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