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参数资料
| 型号： | ADP150CB-3.3-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION 3.3V WLCSP |
| 设计资源： | Broadband Low EVM Direct Conversion Transmitter (CN0134) Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144) Using low noise linear drop-out regulators to power wideband PLL & VCO IC's (CN0147) |
| 标准包装： | 1 |
| 每 IC 通道数： | 1 - 单 |
| 输出电压： | 3.3V |
| 电流 - 输出： | 150mA |
| 输入电压： | 2.2 ~ 5.5V |
| 稳压器类型： | 正，固定式 |
| 工作温度： | -40°C ~ 125°C |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP150 |
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND ?0.3 V to +6.5 V
VOUT to GND ?0.3 V to VIN
EN to GND ?0.3 V to +6.5 V
Storage Temperature Range ?65°C to +150°C
Operating Junction Temperature Range ?40°C to +125°C
Operating Ambient Temperature Range ?40°C to +85°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP150 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that T J is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits. The
junction temperature (T J ) of the device is dependent on the
ambient temperature (T A ), the power dissipation of the device (P D ),
ADP150
The junction-to-ambient thermal resistance (θ JA ) of the package
is based on modeling and a calculation using a 4-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ JA can vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θ JA are based on a 4-layer, 4 inch × 3 inch circuit board.
Refer to JESD 51-7 and JESD 51-9 for detailed information
on the board construction. For additional information, see
the AN-617 Application Note, MicroCSP? Wafer Level Chip
Scale Package .
Ψ JB is the junction-to-board thermal characterization parameter
with units of °C/W. Ψ JB of the package is based on modeling and
a calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information , states that
thermal characterization parameters are not the same as thermal
resistances. Ψ JB measures the component power flowing through
multiple thermal paths rather than a single path as in thermal
resistance, θ JB . Therefore, Ψ JB thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make Ψ JB more useful in real-world applications.
Maximum junction temperature (T J ) is calculated from the
board temperature (T B ) and power dissipation (P D ) by
T J = T B + ( P D × Ψ JB )
Refer to JESD51-8 and JESD51-12 for more detailed information
about Ψ JB .
THERMAL RESISTANCE
θ JA and Ψ JB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
and the junction-to-ambient thermal resistance of the package
(θ JA ).
Maximum junction temperature (T J ) is calculated from the
ambient temperature (T A ) and power dissipation (P D ) by
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
4-Ball, 0.4 mm Pitch WLCSP
θ JA
170
260
Ψ JB
43
58
Unit
°C/W
°C/W
T J = T A + ( P D × θ JA )
ESD CAUTION
Rev. B | Page 5 of 20
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