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参数资料
| 型号： | ADP1614ACPZ-1.3-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST ADJ 4A 10LFCSP |
| 标准包装： | 1,500 |
| 类型： | 升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 2.5 V ~ 20 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.3MHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-LFCSP-WD（3x3） |
| 其它名称： | ADP1614ACPZ-1.3-R7-ND ADP1614ACPZ-1.3-R7TR |
V OUT ? V IN ( MAX )
D MIN = (12)
DataSheet
CHOOSING THE INPUT AND OUTPUT CAPACITORS
The ADP1614 requires input and output bypass capacitors to
supply transient currents while maintaining constant input
and output voltages. Use low equivalent series resistance (ESR)
capacitors of 10 μF or greater to prevent noise at the ADP1614
input. Place the capacitor between VIN and GND, as close as
possible to the ADP1614 . Ceramic capacitors are preferable
because of their low ESR characteristics. Alternatively, use a
ADP1614
diode is rated to handle the average output load current with
the minimum duty cycle. The minimum duty cycle in CCM of
the ADP1614 is
V OUT
where V IN(MAX) is the maximum input voltage.
The following are suggested Schottky diode manufacturers:
high value, medium ESR capacitor in parallel with a 0.1 μF low
?
?
ON Semiconductor
Diodes, Inc.
Q C I × t ON
? V OUT =
? V IN
?
R
F Z ( RHP ) = ? ?
? × LOAD (13)
2 π × L
? V OUT
?
The output capacitor maintains the output voltage and supplies
current to the load while the ADP1614 switch is on. The value
and characteristics of the output capacitor greatly affect the
output voltage ripple and stability of the regulator. A low ESR
ceramic dielectric capacitor is preferable. The output voltage
ripple ( ? V OUT ) is calculated as follows:
= OUT (8)
C OUT C OUT
where:
Q C is the charge removed from the capacitor.
C OUT is the output capacitance.
I OUT is the output load current.
t ON is the on time of the switch.
The on time of the switch is determined as follows:
? Toshiba
? ROHM Semiconductor
LOOP COMPENSATION
The ADP1614 uses external components to compensate the
regulator loop, allowing optimization of the loop dynamics for a
given application.
The step-up converter produces an undesirable right-half plane
zero in the regulation feedback loop. This requires compensating
the regulator such that the crossover frequency occurs well below
the frequency of the right-half plane zero. The right-half plane
zero is determined by the following equation:
2
?
t ON =
V ? V IN
D
f SW
The input (V IN ) and output (V OUT ) voltages determine the
switch duty cycle (D) as follows:
D = OUT
V OUT
(9)
(10)
where:
F Z (RHP) is the right-half plane zero.
R LOAD is the equivalent load resistance or the output voltage
divided by the load current.
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-fifth of the right-half
plane zero.
Choose the output capacitor based on the following equation:
The regulator loop gain is
C OUT ≥
I OUT × ( V OUT ? V IN )
f SW × V OUT × ? V OUT
(11)
A VL =
V FB
V OUT
×
V IN
V OUT
× G MEA × R OUT Z COMP × G CS × Z OUT (14)
Multilayer ceramic capacitors are recommended for this
application.
DIODE SELECTION
The output rectifier conducts the inductor current to the output
capacitor and load while the switch is off. For high efficiency,
minimize the forward voltage drop of the diode. For this reason,
using Schottky rectifiers is recommended. However, for high
voltage, high temperature applications, where the Schottky
rectifier reverse leakage current becomes significant and can
degrade efficiency, use an ultrafast junction diode.
Many diode manufacturers derate the current capability of the
diode as a function of the duty cycle. Verify that the output
where:
A VL is the loop gain.
V FB is the feedback regulation voltage, 1.245 V.
V OUT is the regulated output voltage.
V IN is the input voltage.
G MEA is the error amplifier transconductance gain.
R OUT = 67 M?.
Z COMP is the impedance of the series RC network from COMP
to GND.
G CS is the current sense transconductance gain (the inductor
current divided by the voltage at COMP), which is internally
Z OUT is the impedance of the load in parallel with the output
capacitor.
Rev. A | Page 15 of 20
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