参数资料
型号: ADP1870-BL1-EVZ
厂商: Analog Devices Inc
文件页数: 4/44页
文件大小: 0K
描述: EVAL BOARD FOR ADP1870
标准包装: 1
主要目的: DC/DC,步降
稳压器拓扑结构: 降压
板类型: 裸(未填充)
已供物品: 裸板
已用 IC / 零件: ADP1870
ADP1870/ADP1871
Data Sheet
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ADP1870ARMZ-0.6/
ADP1871ARMZ-0.6 (600 kHz)
600
kHz
On-Time
Minimum On-Time
Minimum Off-Time
V IN = 5 V, V OUT = 2 V, T J = 25°C
V IN = 20 V, V OUT = 0.8 V
65% duty cycle (maximum)
500
540
82
340
580
110
400
ns
ns
ns
ADP1870ARMZ-1.0/
ADP1871ARMZ-1.0 (1.0 MHz)
1.0
MHz
On-Time
Minimum On-Time
Minimum Off-Time
V IN = 5 V, V OUT = 2 V, T J = 25°C
V IN = 20 V
45% duty cycle (maximum)
285
312
60
340
340
85
400
ns
ns
ns
OUTPUT DRIVER CHARACTERISTICS
High-Side Driver
Output Source Resistance
Output Sink Resistance
I SOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V)
I SINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V)
2.25
0.7
3
1
Ω
Ω
Rise Time 2
Fall Time 2
t r,DRVH
t f,DRVH
V BST ? V SW = 4.4 V, C IN = 4.3 nF (see Figure 60)
V BST ? V SW = 4.4 V, C IN = 4.3 nF (see Figure 61)
25
11
ns
ns
Low-Side Driver
Output Source Resistance
Output Sink Resistance
I SOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V)
I SINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V)
1.6
0.7
2.2
1
Ω
Ω
Rise Time 2
Fall Time 2
t r,DRVL
t f,DRVL
V REG = 5.0 V, C IN = 4.3 nF (see Figure 61)
V REG = 5.0 V, C IN = 4.3 nF (see Figure 60)
18
16
ns
ns
Propagation Delays
DRVL Fall to DRVH Rise 2
DRVH Fall to DRVL Rise 2
SW Leakage Current
t tpdhDRVH
t tpdhDRVL
I SWLEAK
V BST ? V SW = 4.4 V (see Figure 60)
V BST ? V SW = 4.4 V (see Figure 61)
V BST = 25 V, V SW = 20 V, V REG = 5 V
15.4
18
110
ns
ns
μA
Integrated Rectifier
Channel Impedance
I SINK = 10 mA
22
Ω
PRECISION ENABLE THRESHOLD
Logic High Level
Enable Hysteresis
V IN = 2.9 V to 20 V, V REG = 2.75 V to 5.5 V
V IN = 2.9 V to 20 V, V REG = 2.75 V to 5.5 V
245
285
37
330
mV
mV
COMP VOLTAGE
COMP Clamp Low Voltage
V COMP(low)
From disabled state, release COMP/EN pin to enable
0.47
V
device (2.75 V ≤ V REG ≤ 5.5 V)
COMP Clamp High Voltage
COMP Zero Current Threshold
V COMP(high)
V COMP_ZCT
(2.75 V ≤ V REG ≤ 5.5 V)
(2.75 V ≤ V REG ≤ 5.5 V)
1.07
2.55
V
V
THERMAL SHUTDOWN
T TMSD
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Hiccup Current Limit Timing
Rising temperature
155
15
6
°C
°C
ms
1
2
The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 60 and Figure 61), C GATE = 4.3 nF, and the upper- and lower-side
MOSFETs being Infineon BSC042N03MSG.
Not automatic test equipment (ATE) tested.
Rev. B | Page 4 of 44
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