参数资料
型号: ADP1871ARMZ-0.3-R7
厂商: Analog Devices Inc
文件页数: 29/44页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 10-MSOP
标准包装: 1
PWM 型: 电流模式
输出数: 1
频率 - 最大: 300kHz
占空比: 84%
电源电压: 2.95 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 标准包装
其它名称: ADP1871ARMZ-0.3-R7DKR
? I L ≈
I LOAD
= ( 4 . 62 × ( 300 × 10 × 3 . 3 × 10
× 4 . 62 + 0 . 002 ))
( V IN,MAX ? V OUT ) V OUT
? I L × f SW
( 13 . 2 V ? 1 . 8 V ) 1 . 8 V
= ×
5 V × 300 × 10
13 . 2 V
C IN,min =
I LOAD , MAX 15 A
C OUT = 2 ×
= 2 ×
DataSheet
P DISS ( LDO ) = P DR ( LOSS ) + ( V IN ? V REG ) × ( f SW × C total × V REG + I BIAS ) (4)
where:
P DISS(LDO) is the power dissipated through the pass device in the
LDO block across VIN and VREG.
C total is the C GD + C GS of the external MOSFET.
V REG is the LDO output voltage and bias voltage.
V IN is the high voltage input.
I BIAS is the dc input bias current.
P DR(LOSS) is the MOSFET driver loss.
For example, if the external MOSFET characteristics are θ JA
(10-lead MSOP) = 171.2°C/W, f SW = 300 kHz, I BIAS = 2 mA,
C upperFET = 3.3 nF, C lowerFET = 3.3 nF, V DR = 4.62 V, and V REG = 5.0 V,
then the power loss is
[
P DR ( LOSS ) = V DR × ( f SW C upperFET V DR + I BIAS ) ]
+ [ V REG × ( f SW C lowerFET V REG + I BIAS ) ]
3 ? 9
+ ( 5 . 0 × ( 300 × 10 3 × 3 . 3 × 10 ? 9 × 5 . 0 + 0 . 002 ))
= 57.12 mW
P DISS ( LDO ) = ( V IN ? V REG ) × ( f SW × C total × V REG + I BIAS )
= ( 13 V ? 5 V ) × ( 300 × 10 3 × 3 . 3 × 10 ? 9 × 5 + 0 . 002 )
= 55.6 mW
P DISS ( TOTAL ) = P DISS ( LDO ) + P DR ( LOSS )
= 77 . 13 mW + 55 . 6 mW
= 132.73 mW
The rise in package temperature (for 10-lead MSOP) is
T R = θ JA × P DR ( LOSS )
= 171 . 2 °C × 132 . 05 mW
= 22.7°C
Assuming a maximum ambient temperature environment of 85°C,
T J = T R × T A = 22 . 7 °C + 85 °C = 107 . 72 °C
which is below the maximum junction temperature of 125°C.
DESIGN EXAMPLE
The ADP1870/ADP1871 are easy to use, requiring only a few
design criteria. For example, the example outlined in this section
uses only four design criteria: V OUT = 1.8 V, I LOAD = 15 A (pulsing),
V IN = 12 V (typical), and f SW = 300 kHz.
Input Capacitor
The maximum input voltage ripple is usually 1% of the
minimum input voltage (11.8 V × 0.01 = 120 mV).
V RIPP = 120 mV
V MAX,RIPPLE = V RIPP ? ( I LOAD,MAX × ESR )
= 120 mV ? (15 A × 0.001) = 45 mV
=
4 f SW V MAX , RIPPLE 4 × 300 × 10 3 × 105 mV
= 120 μF
ADP1870/ADP1871
Choose five 22 μF ceramic capacitors. The overall ESR of five
22 μF ceramic capacitors is less than 1 mΩ.
I RMS = I LOAD /2 = 7.5 A
P CIN = ( I RMS ) 2 × ESR = (7.5 A) 2 × 1 mΩ = 56.25 mW
Inductor
Determine inductor ripple current amplitude as follows:
=5A
3
so calculating for the inductor value
L = ×
V IN,MAX
3
= 1.03 μH
The inductor peak current is approximately
15 A + (5 A × 0.5) = 17.5 A
Therefore, an appropriate inductor selection is 1.0 μH with
DCR = 3.3 mΩ (Würth Elektronik 7443552100) from Table 8
with peak current handling of 20 A.
P DCR ( LOSS ) = DCR × I L 2
= 0.003 × (15 A) 2 = 675 mW
Current Limit Programming
The valley current is approximately
15 A ? (5 A × 0.5) = 12.5 A
Assuming a lower-side MOSFET R ON of 4.5 mΩ and 13 A as
the valley current limit from Table 7 and Figure 71 indicates, a
programming resistor (RES) of 100 kΩ corresponds to an A CS
of 24 V/V.
Choose a programmable resistor of R RES = 100 k? for a current-
sense gain of 24 V/V.
Output Capacitor
Assume that a load step of 15 A occurs at the output and no more
than 5% is allowed for the output to deviate from the steady state
operating point. In this case, the ADP1870’s advantage is that
because the frequency is pseudo-fixed, the converter is able to
respond quickly because of the immediate, though temporary,
increase in switching frequency.
Δ V DROOP = 0.05 × 1.8 V = 90 mV
Assuming that the overall ESR of the output capacitor ranges
from 5 mΩ to 10 mΩ,
? I LOAD
f SW × ( ? V DROOP )
15 A
300 × 10 3 × ( 90 mV )
= 1.11 mF
Rev. B | Page 29 of 44
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