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参数资料
| 型号： | ADP1875-0.6-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL 600KHZ ADP1875 |
| 标准包装： | 1 |
| 系列： | * |
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V OUT = 1.8V
V OUT = HIGH SETPOINT
P DISS ( LDO ) =
P DR ( LOSS ) + ( V IN ? VREG ) × ( f SW × C TOTAL × VREG + I BIAS )
DataSheet
THERMAL CONSIDERATIONS
The ADP1874 / ADP1875 are used for dc-to-dc, step down, high
current applications that have an on-board controller, an on-board
LDO, and on-board MOSFET drivers. Because applications may
require up to 20 A of load current and be subjected to high ambient
temperature, the selection of external upper side and lower side
MOSFETs must be associated with careful thermal consideration
to not exceed the maximum allowable junction temperature of
125°C. To avoid permanent or irreparable damage, if the junction
temperature reaches or exceeds 155°C, the part enters thermal
shutdown, turning off both external MOSFETs and is not re-
enabled until the junction temperature cools to 140°C (see the
In addition, it is important to consider the thermal impedance
of the package. Because the ADP1874 / ADP1875 employ an
on-board LDO, the ac current (fxCxV) consumed by the internal
drivers to drive the external MOSFETs, adds another element of
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO.
which are available in a 16-lead QSOP.
Table 9. Thermal Impedance for 16-lead QSOP
Parameter Thermal Impedance
16-Lead QSOP θ JA
4-Layer Board 104°C/W
that can surround the ADP1874 / ADP1875 IC for a specified
high input voltage (V IN ). Figure 89 illustrates the temperature
derating conditions for each available switching frequency for
low, typical, and high output setpoints for the 16-lead QSOP
package. All temperature derating criteria are based on a
maximum IC junction temperature of 125°C.
150
600kHz V OUT = 0.8V
140 300kHz
1MHz
130
120
110
100
90
80
70
ADP1874/ADP1875
ADP1875 ICs is 125°C. This means that the sum of the ambient
temperature (T A ) and the rise in package temperature (T R ), which is
caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by the
following expression:
T J = T R × T A (1)
where:
T J is the maximum junction temperature.
T R is the rise in package temperature due to the power
dissipated from within.
T A is the ambient temperature.
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
T R = θ JA × P DR(LOSS) (2)
where:
θ JA is the thermal resistance of the package from the junction to
the outside surface of the die, where it meets the surrounding air.
P DR(LOSS) is the overall power dissipated by the IC.
The bulk of the power dissipated is due to the gate capacitance of
the external MOSFETs and current running through the on-board
LDO. The power loss equations for the MOSFET drivers and
section and the Efficiency Consideration section) are
P DR(LOSS) = [ V DR × ( f SW C upperFET V DR + I BIAS )] +
[ VREG × ( f SW C lowerFET VREG + I BIAS )] (3)
where:
C upperFET is the input gate capacitance of the upper side MOSFET.
C lowerFET is the input gate capacitance of the lower side MOSFET.
I BIAS is the dc current (2 mA) flowing into the upper side and
lower side drivers.
V DR is the driver bias voltage (the low input voltage (VREG) minus
the rectifier drop (see Figure 87)).
VREG is the LDO output/bias voltage.
(4)
where:
P DISS(LDO) is the power dissipated through the pass device in the
LDO block across VIN and VREG.
60
50
40
30
5.5
7.0
8.5
10.0
11.5
13.0
V IN (V)
14.5
16.0
17.5
19.0
P DR(LOSS) is the MOSFET driver loss.
V IN is the high voltage input.
VREG is the LDO output voltage and bias voltage.
C TOTAL is the C GD + C GS of the external MOSFET.
I BIAS is the dc input bias current.
Figure 89. Ambient Temperature vs. V IN ,
4-Layer EVB, C IN = 4.3 nF (Upper Side/Lower Side MOSFET)
Rev. A | Page 31 of 44
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