参数资料
型号: ADP1878-0.6-EVALZ
厂商: Analog Devices Inc
文件页数: 36/40页
文件大小: 0K
描述: BOARD EVAL FOR ADP1878-0.6
标准包装: 1
系列: *
ADP1878/ADP1879
SW
PGND
Data Sheet
LAYER 1: SENSE LINE FOR SW
(DRAIN OF LOWER MOSFET)
LAYER 1: SENSE LINE FOR PGND
(SOURCE OF LOWER MOSFET)
Figure 91. Primary Current Pathways During the On State of the High-Side
MOSFET (Left Arrow) and the On State of the Low-Side MOSFET (Right Arrow)
DIFFERENTIAL SENSING
Because the ADP1878 / ADP1879 operate in valley current-mode
control, a differential voltage reading is taken across the drain
and source of the low-side MOSFET. Connect the drain of the
low-side MOSFET s as close as possible to the SW pin (Pin 13) of
the IC. Likewise, connect the source as close as possible to the
PGND pin (Pin 11) of the IC. When possible, keep both of
Figure 92. Drain/Source Tracking Tapping of the Low-Side MOSFET for CS
Amp Differential Sensing (Yellow Sense Line on Layer 2)
In addition, employ differential sensing between the outermost
output capacitor and the feedback resistor divider (see Figure 89
and Figure 90). Connect the positive terminal of the output
capacitor to the top resistor (R T ). Connect the negative terminal
of the output capacitor to the negative terminal of the bottom
resistor, which connects to the analog ground plane as well.
Keep both of these track lines, as previously mentioned, narrow
and away from any other active device or voltage/ current path.
these track lines narrow and away from any other active device
or voltage/current path.
Rev. B | Page 36 of 40
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