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参数资料
| 型号： | ADP2102YCPZ-1.25R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC 1.25V 8LFCSP |
| 产品培训模块： | ADP2102 DSP Battery Life Applications |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 1.25V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 3MHz |
| 电流 - 输出： | 600mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-VFDFN 裸露焊盘，CSP |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-LFCSP-VD（3x3） |
| 其它名称： | ADP2102YCPZ-1.25R7DKR |
ADP2102
APPLICATIONS INFORMATION
The external component selection for the ADP2102 applications
circuit, as shown in Figure 2, is driven by the load requirement
and begins with the selection of Inductor L. Once the inductor
is chosen, C IN and C OUT can be selected.
INDUCTOR SELECTION
The high switching frequency of the ADP2102 allows for minimal
output voltage ripple, even with small inductors. Inductor sizing
is a trade-off between efficiency and transient response. A small
inductor leads to a larger inductor current ripple that provides
excellent transient response but degrades efficiency. Due to the
high switching frequency of the ADP2102, multilayer ceramic
inductors can be used for an overall smaller solution size. Shielded
ferrite core inductors are recommended for their low core losses
and low electromagnetic interference (EMI).
As a guideline, the inductor peak-to-peak current ripple, ΔI L ,
is typically set to 1/3 of the maximum load current for optimal
transient response and efficiency.
In principle, different types of capacitors can be considered, but
for battery-powered applications, the best choice is a multilayer
ceramic capacitor, due to its small size and equivalent series
resistance (ESR).
It is recommended that the PVIN pin be bypassed with a 2.2 μF
or larger ceramic input capacitor. The size of the input capacitor
can be increased without any limit for better input voltage filtering.
X5R or X7R dielectrics are recommended, with a voltage rating of
6.3 V or 10 V. Y5U and Z5U dielectrics are not recommended,
due to their poor temperature and dc bias characteristics.
In applications with greater than 300 mA load current, a ceramic
bypass capacitor of 0.01 μF is recommended on the AVIN pin
for better regulation performance.
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the converter. For a given loop
crossover frequency (the frequency at which the loop gain drops
ΔI L =
V OUT × ( V IN ? V OUT )
V IN × f SW × L
≈
I LOAD ( MAX )
3
(7)
to 0 dB), the maximum voltage transient excursion (overshoot) is
inversely proportional to the value of the output capacitor. The
ADP2102 is designed to operate with small ceramic capacitors that
have low ESR and equivalent series inductance (ESL) and are thus
L IDEAL =
V OUT × ( V IN ? V OUT )
V IN × f SW × 0 . 3 × I LOAD ( MAX )
comfortably able to meet tight output voltage ripple specifications.
X5R or X7R dielectrics are recommended with a voltage rating of
6.3 V or 10 V. Y5V and Z5U dielectrics are not recommended,
where f SW is the switching frequency.
Finally, it is important that the inductor be capable of handling
the maximum peak inductor current, I PK , determined by the
following equation:
due to their poor temperature and dc bias characteristics. When
choosing output capacitors, it is also important to account for the
loss of capacitance due to output voltage dc bias. If ceramic output
capacitors are used, the capacitor rms ripple current rating
should always meet the application requirements. The rms ripple
I PK = I LOAD(MAX) + ΔI L /2
(8)
current is calculated as
The dc current rating of the inductor should be at least equal
to the maximum load current plus half the ripple current to
I rms(COUT) =
1
2 3
×
V OUT × ( V IN _ MAX ? V OUT )
L × f SW × V IN _ MAX
(10)
prevent core saturation. Table 5 shows some typical surface
mount inductors that work well in ADP2102 applications.
INPUT CAPACITOR SELECTION
The input capacitor must be able to support the maximum
input operating voltage and the maximum rms input current.
At nominal load currents, the converter operates in forced
continuous conduction mode, and the overall output voltage ripple
is the sum of the voltage spike caused by the output capacitor ESR
plus the voltage ripple caused by charging and discharging the
output capacitor.
The rms input current flowing through the input capacitor is,
ΔV OUT = ΔI L × (ESR + 1/ (8 × C OUT × f SW ))
(11)
at maximum, I OUT /2. Select an input capacitor capable of with-
standing the rms input current for the maximum load current
in the application to be used.
The largest voltage ripple occurs at the highest input voltage,
V IN . At light load currents, the converter operates in power save
mode, and the output voltage ripple is dependent on the output
I rms = I OUTMAX ×
V OUT × ( V IN ? V OUT )
V IN
(9)
capacitor value. The ADP2102 control loop is stable with a ceramic
output capacitor of 2.2 μF. For better transient performance, a 10 μF
ceramic capacitor is recommended at the output. Table 6 lists input
The input capacitor reduces input voltage ripple caused by the
switch currents on the PVIN pin. Place the input capacitor as
and output MLCC capacitors recommended for ADP2102
applications.
close as possible to the PVIN pin.
Page 16 of 24
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