参数资料
型号: ADP2102YCPZ-1.25R7
厂商: Analog Devices Inc
文件页数: 22/24页
文件大小: 0K
描述: IC REG BUCK SYNC 1.25V 8LFCSP
产品培训模块: ADP2102 DSP Battery Life Applications
标准包装: 1
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 1.25V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 3MHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-VFDFN 裸露焊盘,CSP
包装: 标准包装
供应商设备封装: 8-LFCSP-VD(3x3)
其它名称: ADP2102YCPZ-1.25R7DKR

ADP2102
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential in obtaining the best
performance from the ADP2102. Poor circuit layout degrades
the output ripple and regulation, as well as the EMI and
electromagnetic compatibility performance.
Figure 52 and Figure 53 show the ideal circuit board layout for
the typical applications circuit shown in Figure 48. Use this
layout to achieve the highest performance. Refer to the following
guidelines for optimum layout:
? Use separate analog and power ground planes. Connect the
ground reference of sensitive analog circuitry, such as output
voltage divider components, to analog ground. In addition,
connect the ground references of power components, such as
input and output capacitors, to power ground. Connect both
ground planes to the exposed pad of the ADP2102.
? Place the input capacitor as close to the PVIN pin as possible
and connect the other end to the closest power ground plane.
? For low noise and better transient performance, a filter is
recommended between PVIN and AVIN. Place the 0.1 μF,
10 Ω low-pass input filter between the AVIN pin and the
PVIN pin, as close to AVIN as possible; or the AVIN pin can
be bypassed with a ≥1 pF capacitor to the nearest GND plane.
RECOMMENDED LAYOUT
VIN
?
?
Ensure that the high current loops are as short and as wide
as possible. Make the high current path from C IN through L,
C OUT , and the PGND plane back to C IN as short as possible.
To accomplish this, ensure that the input and output capacitors
share a common PGND plane. In addition, make the high
current path from the PGND pin through L and C OUT back
to the PGND plane as short as possible. To do this, ensure
that the PGND pin of the ADP2102 is tied to the PGND
plane as close as possible to the input and output capacitors.
Place the feedback resistor divider network as close as possible
to the FB pin to prevent noise pickup. Try to minimize the
length of trace connecting the top of the feedback resistor
divider to the output while keeping away from the high
current traces and the switch node (LX) that can lead to
noise pickup. To reduce noise pickup, place an analog ground
plane on either side of the FB trace and make it as small as
possible to reduce the parasitic capacitance pickup.
PGND
MODE
9 mm
EN
CBP
CIN
COUT
VOUT
FB/OUT
8 mm
AGND
ADP2102
L1
INDUCTOR
Figure 51. Recommended PCB Layout of the ADP2102-FXD
Rev. B | Page 22 of 24
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参数描述
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