参数资料
型号: ADP2102YCPZ-3-R7
厂商: Analog Devices Inc
文件页数: 14/24页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.6A 8LFCSP
产品培训模块: ADP2102 DSP Battery Life Applications
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.5 V ~ 1.88 V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 3MHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-VFDFN 裸露焊盘,CSP
包装: 标准包装
供应商设备封装: 8-LFCSP-VD(3x3)
产品目录页面: 791 (CN2011-ZH PDF)
配用: ADP2102-4-EVALZ-ND - BOARD EVAL 2.5V-3.3V ADJ OUTPUT
ADP2102-3-EVALZ-ND - BOARD EVAL 1.5V-1.875V ADJ OUTPT
ADP2102-2-EVALZ-ND - BOARD EVAL 1.2V-1.5V ADJ OUTPUT
ADP2102-1-EVALZ-ND - BOARD EVAL 0.8V-1.2V ADJ OUTPUT
ADP2102-1.8-EVALZ-ND - BOARD EVAL FOR ADP2102-1.8
ADP2102-1.875EVALZ-ND - BOARD EVAL FOR ADP2102-1.875
ADP2102-1.5-EVALZ-ND - BOARD EVAL FOR ADP2102-1.5
ADP2102-1.375EVALZ-ND - BOARD EVAL FOR ADP2102-1.375
ADP2102-1.25-EVALZ-ND - BOARD EVAL FOR ADP2102-1.25
ADP2102-1.0-EVALZ-ND - BOARD EVAL FOR ADP2102-1.0
更多...
其它名称: ADP2102YCPZ-3-R7DKR
ADP2102
As a result of this auto mode control technique, losses are
minimized at light loads, improving system efficiency.
The PSM reverse current comparator controls the entry and exit
into forced continuous conduction mode. Some minor jitter is
normal during transition from DCM to CCM with loads at
approximately 100 mA typical, and it has no adverse impact on
regulation.
SYNCHRONOUS RECTIFICATION
When the load current is further increased such that the lower
peak is above the current limit threshold, the off time is lengthened
to allow the current to decrease to this threshold before the next
on-time begins.
Both V OUT and the switching frequency are reduced as the circuit
operates in constant current mode. The load current (I OCL ) under
these conditions is equal to the current limit threshold plus half
the ripple current, as shown in Equation 5 and in Figure 44.
In addition to the P-channel MOSFET switch, the ADP2102
includes an integrated N-channel MOSFET synchronous recti-
fier. The synchronous rectifier improves efficiency, especially
at low output voltages, and reduces cost and board space by
eliminating the need for an external rectifier.
I OCL = I VALLEY + Δ I L /2
DC CURRENT LIMIT = MAX LOAD
(5)
CURRENT LIMIT
The current limit circuit employs a valley current sensing scheme.
Current limit detection occurs during the off time through
sensing of the voltage drop across the on resistance of the
synchronous rectifier switch. The detection threshold is 1 A
typical.
INDUCTOR
CURRENT
I OCL
VALLEY CURRENT LIMIT
Figure 44. Valley Current Limit
TIME
Δ I
Figure 45 illustrates the inductor current waveform during normal
operation and during current limit. The output current, I OUT ,
The ripple current is calculated using Equation 6.
is the average of the inductor ripple current waveform. The
low-to-medium load current waveform illustrates the continuous
conduction mode operation with peak and valley inductor
Δ I L =
V OUT × ( V IN ? V OUT )
V IN × f SW × L
(6)
currents below the current limit threshold. When the load
current is increased, the ripple waveform maintains the same
amplitude and frequency because the current falls below the
current limit threshold at the valley of the ripple waveform.
As the current falls below the threshold during the normal off-
The ADP2102 also provides a negative current limit to prevent
an excessive reverse inductor current when the switching section
sinks current from the load in forced continuous conduction
mode. Under negative current limit conditions, both the high-
side and low-side switches are disabled.
time of each cycle, the start of each on-time is not delayed, and
the circuit output voltage is regulated at the correct value.
I PEAK
I OCL
CURRENT LIMIT
THRESHOLD
I VALLEY
INDUCTOR
CURRENT
I OUT
Δ I
MEDIUM LOAD
CURRENT
HIGH LOAD
CURRENT
CURRENT LIMIT
NORMAL OPERATION
Figure 45. Inductor Current—Current Limit Operation
Rev. B | Page 14 of 24
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