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| 型号： | ADP2107-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADP2107 |
| 产品培训模块： | Powering 90nm/65nm FPGAs and Processors |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 2.5V |
| 电流 - 输出： | 2A |
| 输入电压： | 2.7 ~ 5.5 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 1.2MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP2107 |
| 相关产品： | ADP2107ACPZ-R7DKR-ND - IC REG BUCK SYNC ADJ 2A 16LFCSP ADP2107ACPZ-3.3-R7DKR-ND - IC REG BUCK SYNC 3.3V 2A 16LFCSP ADP2107ACPZ-1.8-R7DKR-ND - IC REG BUCK SYNC 1.8V 2A 16LFCSP ADP2107ACPZ-1.5-R7DKR-ND - IC REG BUCK SYNC 1.5V 2A 16LFCSP ADP2107ACPZ-1.2-R7DKR-ND - IC REG BUCK SYNC 1.2V 2A 16LFCSP ADP2107ACPZ-R7CT-ND - IC REG BUCK SYNC ADJ 2A 16LFCSP ADP2107ACPZ-3.3-R7CT-ND - IC REG BUCK SYNC 3.3V 2A 16LFCSP ADP2107ACPZ-1.8-R7CT-ND - IC REG BUCK SYNC 1.8V 2A 16LFCSP ADP2107ACPZ-1.5-R7CT-ND - IC REG BUCK SYNC 1.5V 2A 16LFCSP ADP2107ACPZ-1.2-R7CT-ND - IC REG BUCK SYNC 1.2V 2A 16LFCSP 更多... |
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Data Sheet
used in parallel to ensure that the output capacitance is sufficient
under all conditions for stable behavior.
Table 10. Recommended Input and Output Capacitor
Selection for the ADP2105/ADP2106/ADP2107
ADP2105/ADP2106/ADP2107
LOOP COMPENSATION
The ADP2105/ADP2106/ADP2107 utilize a transconductance
error amplifier to compensate the external voltage loop. The
open loop transfer function at angular frequency (s) is given by
H ( s ) = G m G CS ? ? COMP
? Z ( s ) ? ? V REF
? ?
?
?
Capacitor
4.7 μF, 10 V
Vendor
Murata Taiyo Yuden
GRM21BR61A475K LMK212BJ475KG
? ?
? sC OUT ? ? V OUT
?
?
? ? 1 + sR COMP C COMP
1
Z COMP ( s ) = ? ? R COMP +
? = ?
?
sC COMP
sC COMP
?
? ?
?
? ( 2 π ) F CROSS ? ? C OUT V OUT
Z COMP ( F CROSS ) = ?
? ?
?
? G G
V REF
? ?
? ? ?
( 2 π ) ? ? CROSS ? ? R COMP C COMP = 1
X5R 0805
10 μF, 10 V GRM21BR61A106K LMK212BJ106KG
X5R 0805
22 μF, 6.3 V GRM21BR60J226M JMK212BJ226MG
X5R 0805
INPUT CAPACITOR SELECTION
The input capacitor reduces input voltage ripple caused by the
switch currents on the PWIN pins. Place the input capacitors as
close as possible to the PWIN pins. Select an input capacitor
capable of withstanding the rms input current for the maximum
load current in your application.
For the ADP2105, it is recommended that each PWIN pin be
bypassed with a 4.7 μF or larger input capacitor. For the ADP2106,
bypass each PWIN pin with a 10 μF and a 4.7 μF capacitor, and
for the ADP2107, bypass each PWIN pin with a 10 μF capacitor.
As with the output capacitor, a low ESR ceramic capacitor is
recommended to minimize input voltage ripple. X5R or X7R
dielectrics are recommended, with a voltage rating of 6.3 V or
10 V. Y5V and Z5U dielectrics are not recommended due to
their poor temperature and dc bias characteristics. Refer to
INPUT FILTER
The IN pin is the power source for the ADP2105/ADP2106/
ADP2107 internal circuitry, including the voltage reference and
current sense amplifier that are sensitive to power supply noise.
To prevent high frequency switching noise on the PWIN pins from
corrupting the internal circuitry of the ADP2105/ADP2106/
ADP2107, a low-pass RC filter should be placed between the IN
pin and the PWIN1 pin. The suggested input filter consists of
a small 0.1 μF ceramic capacitor placed between IN and AGND
and a 10 Ω resistor placed between IN and PWIN1. This forms a
150 kHz low-pass filter between PWIN1 and IN that prevents any
high frequency noise on PWIN1 from coupling into the IN pin.
SOFT START PERIOD
To set the soft start period, connect a soft start capacitor (C SS ) from
SS to AGND. The soft start period varies linearly with the size
of the soft start capacitor, as shown in the following equation:
where:
V REF is the internal reference voltage (0.8 V).
V OUT is the nominal output voltage.
Z COMP (s) is the impedance of the compensation network at the
angular frequency.
C OUT is the output capacitor.
g m is the transconductance of the error amplifier (50 μA/V
nominal).
G CS is the effective transconductance of the current loop.
G CS = 1.875 A/V for the ADP2105.
G CS = 2.8125 A/V for the ADP2106.
G CS = 3.625 A/V for the ADP2107.
The transconductance error amplifier drives the compensation
network that consists of a resistor ( R COMP ) and capacitor ( C COMP )
connected in series to form a pole and a zero, as shown in the
following equation:
? ?
? ? ?
At the crossover frequency, the gain of the open loop transfer
function is unity. For the compensation network impedance at
the crossover frequency, this yields the following equation:
?
? m CS ?
where:
F CROSS = 80 kHz, the crossover frequency of the loop.
section.
To ensure that there is sufficient phase margin at the crossover
frequency, place the compensator zero at 1/4 of the crossover
frequency, as shown in the following equation:
F
? 4 ?
Solving the three equations in this section simultaneously yields
the value for the compensation resistor and compensation
capacitor, as shown in the following equation:
R COMP = 0 . 8 ? ?
C COMP =
V REF
? ?
?
?
T SS = C SS × 10 9 ms
For a soft start period of 1 ms, a 1 nF capacitor must be
connected between SS and AGND.
? (2 π ) F CROSS
? G m G CS
2
π F CROSS R COMP
? ?
? ? C OUT V OUT
? ?
?
?
Rev. D | Page 19 of 36
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