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参数资料
| 型号： | ADP2121-1.8-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION 1.8V ADP2121 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.8V |
| 电流 - 输出： | 600mA |
| 输入电压： | 2.3 ~ 5.5 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 6MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP2121 |
ADP2121
OUTPUT VOLTAGE (20mV/DIV, 1.82V DC OFFSET)
repeats. The output voltage, switching node voltage, and
OUTPUT VOLTAGE (20mV/DIV, 1.82V DC OFFSET)
SWITCH NODE VOLTAGE (1V/DIV)
SWITCH NODE VOLTAGE
(2V/DIV)
INDUCTOR CURRENT (200mA/DIV)
V IN = 3.6V
V OUT = 1.82V
I OUT = 200mA
TIME (100ns/DIV)
Figure 52. Typical PWM Operation
INDUCTOR CURRENT
(200mA/DIV)
V IN = 3.6V
V OUT = 1.82V
I OUT = 25mA
Auto Mode (PFM and PWM Switching)
Auto mode is a power-saving feature that enables the converter
to switch between PWM and PFM in response to the output
load. Auto mode is enabled when the MODE pin is pulled low.
In auto mode, the ADP2121 operates in PFM mode for light load
currents and switches to PWM mode for medium and heavy load
currents. Figure 53 uses the typical threshold values of the 1.82 V
output voltage option to demonstrate the behavior of the ADP2121
in auto mode. The threshold values will shift accordingly for other
output voltages.
MODE TRANSITION POINT*
I OUT = 70mA TO 170mA (TYPICAL)
1.875V
OUTPUT VOLTAGE (V)
1.820V
TIME (μs)
INDUCTOR CURRENT (mA)
TIME (1μs/DIV)
Figure 54. Typical PFM Operation
Mode Transition
When the MODE pin is low, the converter switches between
PFM and PWM modes automatically to maintain optimal
transient response and efficiency. The mode transition point
depends on the input voltage. Hysteresis exists in the transition
point to prevent instability and decreased efficiencies that could
result if the converter were able to oscillate between PFM and
A switch from PFM to PWM occurs when the output voltage dips
below the nominal value of the output voltage option. Switching
to PWM allows the converter to maintain efficiency and supply
a larger current to the load.
The switch from PWM to PFM occurs when the output current
is below the PFM threshold for multiple consecutive switching
cycles. Switching to PFM allows the converter to save power by
0mA
TIME (μs)
supplying the lighter load current with fewer switching cycles.
*PFM AND PWM THRESHOLD VARIES WITH INPUT VOLTAGE.
SEE FIGURE 22, FIGURE 23 and FIGURE 24 FOR TYPICAL VALUES.
Figure 53. PFM-to-PWM Transition Point, V OUT = 1.82 V
Pulse Frequency Modulation (PFM)
When the converter is operating under light load conditions,
the effective switching frequency and supply current are
decreased and varied using PFM to regulate the output voltage.
This results in improved efficiencies and lower quiescent
currents. In PFM mode, the converter only switches when
necessary to keep the output voltage within the PFM limits set
by an internal comparator (see Figure 53). Switching stops
when the upper limit is reached and resumes when the lower
limit is reached.
When the upper level is reached, the output stage and oscillator
turn off to reduce the quiescent current. During this stage, the
output capacitor supplies the current to the load. As the output
capacitor discharges and the output voltage reaches the lower
PFM comparator threshold, switching resumes and the process
higher to keep the ADP2121 from oscillating between modes,
ensuring stable operation.
ENABLE/SHUTDOWN
The EN input turns the ADP2121 on or off. Connect EN to
GND or logic low to shut down the part and reduce the current
consumption to 1.0 μA (maximum). Connect EN to VIN or to
logic high to enable the part. Do not leave this pin floating.
INTERNAL CONTROL FEATURES
Overcurrent Protection
To ensure that excessively high currents do not damage the
inductor, the ADP2121 incorporates cycle-by-cycle overcurrent
protection. This function is accomplished by monitoring the
instantaneous peak current on the power PMOS switch. If this
current exceeds the maximum level (1 A typical), the PMOS is
immediately turned off. This minimizes the potential for damage
to power components during certain faults and transient events.
The value listed in Table 2 is an open loop dc tested value. Inherent
Rev. B | Page 15 of 20
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