参数资料
型号: ADP2147ACBZ-110-R7
厂商: Analog Devices Inc
文件页数: 4/16页
文件大小: 0K
描述: IC REG BUCK SYNC 0.8A 6WLCSP
产品变化通告: 8mm Carrier Tape Changes 28/Feb/2012
标准包装: 1
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 1.275V,0.981V
输入电压: 2.3 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 3MHz
电流 - 输出: 800mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-UFBGA,WLCSP
包装: 标准包装
供应商设备封装: 6-WLCSP(1.03x1.50)
其它名称: ADP2147ACBZ-110-R7DKR

ADP2147
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN, EN, VSEL
VOUT, SW to GND
Temperature Range
Operating Ambient
Operating Junction
Storage Temperature
Lead Temperature Range
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
ESD Model
Human Body
Charged Device
Machine
Rating
?0.4 V to +6.5 V
?1.0 V to (V IN + 0.2 V)
?40°C to +85°C
?40°C to +125°C
?65°C to +150°C
?65°C to +150°C
300°C
215°C
220°C
±1500 V
±500 V
±100 V
Junction-to-ambient thermal resistance (θ JA ) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ JA may vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θ JA are based on a 4-layer, 4 in. × 3 in. circuit board. Refer
to JEDEC JESD 51-9 for detailed information pertaining to board
construction. For additional information, see the AN-617
Application Note, MicroCSP? Wafer Level Chip Scale Package .
Ψ JB is the junction-to-board thermal characterization parameter
measured in units of °C/W. The package Ψ JB is based on modeling
and calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information , states that
thermal characterization parameters are not the same as thermal
resistances. Ψ JB measures the component power flowing through
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP2147 can be damaged if the junction temperature limit is
exceeded. Monitoring ambient temperature does not guarantee
that the junction temperature (T J ) is within the specified
multiple thermal paths rather than through a single path, which
is the procedure for measuring thermal resistance, θ JB . There-
fore, Ψ JB thermal paths include convection from the top of the
package as well as radiation from the package, factors that make
Ψ JB more useful in real-world applications than θ JB . Maximum
junction temperature (T J ) is calculated from the board temperature
(T B ) and power dissipation (P D ) using the formula:
T J = T B + ( P D × Ψ JB )
Refer to JEDEC JESD51-8 and JESD51-12 for more detailed
information about Ψ JB .
THERMAL RESISTANCE
θ JA and Ψ JB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
temperature limit. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated. In applications with moderate power
dissipation and low printed circuit board (PCB) thermal
Table 4. Thermal Resistance
Package Type
6-Ball WLCSP
θ JA
170
Ψ JB
80
Unit
°C/W
resistance, the maximum ambient temperature can exceed the
maximum limit if the junction temperature is within specification
limits. The junction temperature (T J ) of the device is dependent
ESD CAUTION
on the ambient temperature (T A ), the power dissipation of the
device (P D ), and the junction-to-ambient thermal resistance of the
package (θ JA ). Maximum junction temperature (T J ) is calculated
from the ambient temperature (T A ) and power dissipation (P D )
using the following formula:
T J = T A + ( P D × θ JA )
Rev. 0 | Page 4 of 16
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