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参数资料
| 型号： | ADP2302ARDZ-3.3-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK 3.3V 2A 8SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 3.3V |
| 输入电压： | 3 V ~ 20 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 700kHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOIC-EP |
| 其它名称： | ADP2302ARDZ-3.3-R7DKR |
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Data Sheet
Table 5. Correlation Between f SW and V FB
ADP2302/ADP2303
OVERVOLTAGE PROTECTION (OVP)
FB Pin Voltage
V FB ≥ 0.6 V
0.4 V < V FB < 0.6 V
0.2 V < V FB ≤ 0.4 V
V FB ≤ 0.2 V
Switching Frequency
f SW
1/2 f SW
1/4 f SW
1/8 f SW
The ADP2302/ADP2303 provide an overvoltage protection
feature to protect the system against an output short to a higher
voltage supply. If the feedback voltage is above 0.880 V, the
internal high-side MOSFET is turned off, until the voltage at FB
decreases to 0.850 V. At that time, the ADP2302/ADP2303
When a hard short (V FB ≤ 0.2 V) is removed, a soft start cycle
is initiated to regulate the output back to its level during normal
operation, which helps to limit the inrush current and prevent
possible overshoot on the output voltage.
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP2302/ADP2303 have fixed, internally set undervoltage
lockout circuitry (UVLO). If the input voltage drops below
2.4 V, the ADP2302/ADP2303 shut down and the MOSFET
switch turns off. After the voltage rises above 2.7 V, the soft
start period is initiated, and the part is enabled.
THERMAL SHUTDOWN (TSD)
If the ADP2302/ADP2303 junction temperature rises above 150 ? C,
the thermal shutdown circuit disables the chip. Extreme junction
temperature can be the result of high current operation, poor
circuit board design, or high ambient temperature. A 15 ? C
resume normal operation.
POWER GOOD
The PGOOD pin is an active high, open-drain output and
requires a resistor to pull it up to a voltage (<20.0 V). A high
indicates that the voltage on the FB pin (and therefore the
output voltage) is above 87.5% of the reference voltage. A low
indicates that the voltage on the FB pin is below 85% of the
reference voltage. There is a 32-cycle waiting period after FB is
detected as being in or out of bounds.
CONTROL LOOP
The ADP2302/ADP2303 are internally compensated to minimize
external component count and cost. In addition, the built-in
slope compensation helps to prevent subharmonic oscillations
when the ADP2302/ADP2303 operate at a duty cycle greater
than or close to 50%.
hysteresis is included so that when thermal shutdown occurs,
the ADP2302/ADP2303 do not return to operation until the on-
chip temperature drops below 135 ? C. When the devices recover
from thermal shutdown, a soft start is initiated.
Rev. A | Page 15 of 28
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