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参数资料
| 型号： | ADP2323-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ADP2323 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 1.2V，3.3V |
| 电流 - 输出： | 3A，3A |
| 输入电压： | 4.5 ~ 20 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 250kHz ~ 1.2MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP2323 |
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T SS =
f SW [kHz] =
ADP2323
BOOTSTRAP CIRCUITRY
The ADP2323 integrates the boot regulators to provide the gate
drive voltage for the high-side NFETs. The regulators generate 5
V bootstrap voltages between the BSTx pin and the SWx pin.
It is recommended that an X7R or an X5R, 0.1 μF ceramic
capacitor be placed between the BSTx and the SWx pins.
LOW-SIDE DRIVER
The DLx pin provides the gate drive for the low-side N-channel
MOSFET. Internal circuitry monitors the gate driver signal to
ensure break-before-make switching to prevent cross
conduction.
The VDRV pin provides the power supply to the low-side
drivers. It is limited to a 5.5 V maximum input, and placing
a 1 μF ceramic capacitor close to this pin is recommended.
OSCILLATOR
A resistor from RT to GND programs the switching frequency
according to the following equation:
60 , 000
R OSC [ kΩ ]
A 200 k? resistor sets the frequency to 300 kHz, and a 100 k?
resistor sets the frequency to 600 kHz. Figure 42 shows the
typical relationship between f SW and R OSC .
1200
1100
1000
900
800
700
600
Data Sheet
When the SYNC pin is configured as an output, it generates a
clock with a frequency that is equal to the internal switching
frequency.
When the SYNC pin is configured as an input, the ADP2323
synchronizes to the external clock that is applied to the SYNC pin,
and the internal clock must be programmed lower than the
external clock. The phase shift can be programmed by the SCFG
pin.
When working in synchronization mode, the ADP2323 disables
the PFM mode and works only in the CCM mode.
SOFT START
The SSx pins are used to program the soft start time. Place a
capacitor between SSx and GND; an internal current charges
this capacitor to establish the soft start ramp. The soft start time
can be calculated using the following equation:
0 . 6 V × C SS
I SS
where:
C SS is the soft start capacitance.
I SS is the soft start pull-up current (3.5 μA).
If the output voltage is precharged prior to power up, the
ADP2323 prevents the low-side MOSFET from turning on until
the soft start voltage exceeds the voltage on the FBx pin.
During soft start, the ADP2323 uses frequency foldback to
prevent output current runaway. The switching frequency is
reduced according to the voltage present at the FBx pin, which
allows more time for the inductor to discharge. The correlation
between the switching frequency and the FBx pin voltage is listed
Table 6. FBx Pin Voltage and Switching Frequency
500
400
300
200
FBx Pin Voltage
V FB ≥ 0.4 V
0.4 V > V FB ≥ 0.2 V
V FB < 0.2 V
Switching Frequency
f SW
1/2 f SW
1/4 f SW
50
70
90
110
130
150
170
190
210
230
250
R OSC (k?)
Figure 42. f SW vs. R OSC
SYNCHRONIZATION
The SYNC pin can be configured as an input or an output by
Table 5. SCFG Configuration
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2323 uses a peak current-limit protection circuit to
prevent current runaway. Place a resistor between DLx and
PGND to program the current-limit value listed in Table 7. The
programmable current-limit threshold feature allows for the use
of a small size inductor for low current applications.
SCFG
High
GND
180 k? to GND
100 k? to GND
SYNC
Output
Input
Input
Input
Phase Shift
0°
90°
120°
60°
Table 7. Peak Current-Limit Threshold Setting
R ILIM Peak Current-Limit Threshold
Floating 4.8 A
47 k? 3A
15 k? 1.5 A
Rev. A | Page 16 of 32
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