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参数资料
| 型号： | ADP322ACPZ-115-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/24页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3.3/2.8/1.8V 16LFCSP |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3.3V，2.8V，1.8V |
| 输入电压： | 1.8 V ~ 5.5 V |
| 电压 - 压降（标准）： | 0.11V @ 200mA，0.11V @ 200mA，- |
| 稳压器数量： | 3 |
| 电流 - 输出： | 200mA（最小值） |
| 电流 - 限制（最小）： | 250mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-WQ（3x3） |
| 包装： | 标准包装 |
| 其它名称： | ADP322ACPZ-115-R7DKR |
Data Sheet
ABSOLUTE MAXIMUM RATINGS
ADP322/ADP323
Table 3.
Parameter
VIN1/VIN2, VIN3, VBIAS to GND
VOUT1, VOUT2, FB1, FB2 to GND
VOUT3, FB3 to GND
EN1, EN2, EN3 to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
–0.3 V to +6.5 V
–0.3 V to VIN1/VIN2
–0.3 V to VIN3
–0.3 V to +6.5 V
–65°C to +150°C
–40°C to +125°C
JEDEC J-STD-020
Junction-to-ambient thermal resistance (θ JA ) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θ JA are based on a 4-layer, 4 inch × 3 inch
circuit board. See JEDEC JESD 51-9 for detailed information
on the board construction. For additional information, see the
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP322/ADP323 triple LDO can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that the junction temperature
(T J ) is within the specified temperature limits. In applications
with high power dissipation and poor thermal resistance, the
maximum ambient temperature may have to be derated. In
applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits.
The junction temperature (T J ) of the device is dependent on the
ambient temperature (T A ), the power dissipation of the device
(P D ), and the junction-to-ambient thermal resistance of the
AN-617 Application Note, MicroCSP? Wafer Level Chip Scale
Package .
Ψ JB is the junction to board thermal characterization parameter
with units of °C/W. Ψ JB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Package Thermal Information , states that
thermal characterization parameters are not the same as thermal
resistances. Ψ JB measures the component power flowing through
multiple thermal paths rather than a single path as in thermal
resistance, θ JB . Therefore, Ψ JB thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make Ψ JB more useful in real-world applications.
Maximum junction temperature (T J ) is calculated from the board
temperature (T B ) and power dissipation (P D ) using the following
formula:
T J = T B + ( P D × Ψ JB )
See JEDEC JESD51-8 and JESD51-12 for more detailed inform-
ation about Ψ JB .
THERMAL RESISTANCE
θ JA and Ψ JB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4.
package (θ JA ). Maximum junction temperature (T J ) is calculated
from the ambient temperature (T A ) and power dissipation (P D )
Package Type
16-Lead, 3 mm × 3 mm LFCSP
θ JA
49.5
Ψ JB
25.2
Unit
°C/W
using the following formula:
T J = T A + ( P D × θ JA )
ESD CAUTION
Rev. A | Page 5 of 24
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