参数资料
型号: ADP322ACPZ-135-R7
厂商: Analog Devices Inc
文件页数: 16/24页
文件大小: 0K
描述: IC REG LDO 3.3/2.5/1.8V 16LFCSP
标准包装: 1
稳压器拓扑结构: 正,固定式
输出电压: 3.3V,2.5V,1.8V
输入电压: 1.8 V ~ 5.5 V
电压 - 压降(标准): 0.11V @ 200mA,0.11V @ 200mA,-
稳压器数量: 3
电流 - 输出: 200mA(最小值)
电流 - 限制(最小): 250mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-WFQFN 裸露焊盘,CSP
供应商设备封装: 16-LFCSP-WQ(3x3)
包装: 标准包装
其它名称: ADP322ACPZ-135-R7DKR

ADP322/ADP323
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP322/ADP323 are designed for operation with small,
space-saving ceramic capacitors, but the parts function with
most commonly used capacitors as long as care is taken with
the effective series resistance (ESR) value. The ESR of the
output capacitor affects the stability of the LDO control loop.
A minimum of 0.70 μF capacitance with an ESR of 1 Ω or less is
recommended to ensure the stability of the ADP322/ADP323.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP322/ADP323 to large
changes in the load current. Figure 46 shows the transient
response for an output capacitance value of 1 μF.
I LOAD1
1
Data Sheet
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN1/VIN2, VIN3, and
VBIAS to GND reduces the circuit sensitivity to the PCB layout,
especially when long input traces or high source impedance is
encountered. If an output capacitance greater than 1 μF is
required, the input capacitor should be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitor can be used with the ADP322/
ADP323, as long as the capacitor meets the minimum capacit-
ance and maximum ESR requirements. Ceramic capacitors are
manufactured with a variety of dielectrics, each with a different
behavior over temperature and applied voltage. Capacitors must
have an adequate dielectric to ensure the minimum capacitance
over the necessary temperature range and dc bias conditions.
X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are
recommended. Y5V and Z5U dielectrics are not recommended
due to their poor temperature and dc bias characteristics.
Figure 47 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 μF, 10 V, X5R capacitor. The voltage stability of a
2
3
4
V OUT1
V OUT2
V OUT3
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or with a higher
voltage rating exhibits better stability. The temperature variation
of the X5R dielectric is about ±15% over the ?40°C to +85°C
temperature range and is not a function of the package or
voltage rating.
1.2
W
CH1 100mA ? BW CH2 50mV
B
M40μs
A CH1
44mA
W
W
CH3 10mV
B
CH4 10mV
B
T 9.8%
1.0
Figure 46. Output Transient Response,
I LOAD1 = 1 mA to 200 mA, I LOAD2 = 1 mA, I LOAD3 = 1 mA,
CH1 = I LOAD1 , CH2 = V OUT1 , CH3 = V OUT2 , CH4 = V OUT3
0.8
0.6
0.4
0.2
0
0
2
4 6
8
1 0
VOLTAGE (V)
Figure 47. Capacitance vs. Voltage Bias Characteristic
Rev. A | Page 16 of 24
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