参数资料
| 型号： | ADP3367ARZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V/ADJ .2A 8SOIC |
| 标准包装： | 98 |
| 稳压器拓扑结构： | 正，固定式或可调式 |
| 输出电压： | 5V，1.3 V ~ 16 V |
| 输入电压： | 2.5 V ~ 16.5 V |
| 电压 - 压降（标准）： | 0.3V @ 300mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 200mA（最小值） |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 795 (CN2011-ZH PDF) |
ADP3367
V IN
+
IN
OUT
ADP3367
+
C1
10μF
R2
10k ?
+5V
OUTPUT
reached, the DD output starts sourcing current into the SET
input through R3. This increases the SET voltage so that the
regulator feedback loop does not drive the internal PNP transis-
LBI
SET
LBO
DD
GND SHDN
DROPOUT
STATUS
OUTPUT
tor as hard as it otherwise would. As the input voltage continues
to decrease, more current is sourced, thereby reducing the PNP
drive even further. The advantage of this scheme is that it main-
tains a low quiescent current down to very low values of V IN at
which point the batteries are well outside their useful operating
range. The output voltage tracks the input voltage minus the
R1
100k ?
dropout. The SHDN function is also unaffected and may be
used normally if desired.
Figure 11. Dropout Status Output
Output Capacitor
V IN
+
IN
OUT
ADP3367
R2
2M ?
+ C1
10μF
+5V
OUTPUT
An output capacitor is required on the ADP3367 to maintain sta-
SHDN
SET
bility and also to improve the load transient response. Capacitor
values from 10 μ F upwards are recommended. Capacitors larger
than 10 μ F will further improve the transient response. Tantalum
or aluminum electrolytics are suitable for most applications. For
temperatures below about –25 ° C, solid tantalums should be used
GND
DD
R3
1M ?
R1
610k ?
as many aluminum electrolytes freeze at this temperature.
Quiescent Current Considerations
The ADP3367 uses a PNP output stage to achieve low dropout
voltages combined with high output current capability. Under
normal regulating conditions the quiescent current is extremely
low. However if the input voltage drops so that it is below the
desired output voltage, the quiescent current increases consider-
ably. This happens because regulation can no longer be main-
tained and large base current flows in the PNP output transistor
in an attempt to hold it fully on. For minimum quiescent cur-
rent, it is therefore important that the input voltage is main-
tained higher than the desired output level. If the device is being
1mA
900
800
700
600
500μA
400
300
200
100
1.2mA
900μA
powered using a battery that can discharge down below the rec-
ommended level, there are a couple of techniques that can be
applied to reduce the quiescent current, but at the expense of
0
1
2 3 4 5
V IN – V
QUIESCENT CURRENT BELOW DROPOUT
6
dropout voltage. The first of these is illustrated in Figure 12. By
connecting DD to SHDN the regulator is partially disabled with
input voltages below the desired output voltage and therefore
the quiescent current is reduced considerably.
Figure 13. IQ Reduction 2
POWER DISSIPATION
The ADP3367 can supply currents up to 300 mA and can oper-
V IN
+
IN
OUT
ADP3367
+ C1
10μF
+5V
OUTPUT
ate with input voltages as high as 16.5 V, but not simultaneously.
It is important that the power dissipation and hence the internal
die temperature be maintained below the maximum limits. Power
DD
Dissipation is the product of the voltage differential across the
SET
GND SHDN
regulator times the current being supplied to the load. The
maximum package power dissipation is given in the Absolute
R1
47k ?
C2
0.1μF
Maximum Ratings. In order to avoid excessive die temperatures,
these ratings must be strictly observed.
Figure 12. IQ Reduction 1
Another technique for reducing the quiescent current near drop-
out is illustrated in Figure 13. The DD output is used to modify
the output voltage so that as V IN drops, the desired output volt-
age setpoint also drops. This technique only works when exter-
nal resistors are used to set the output voltage. With V IN greater
than V OUT , DD has no effect. As V IN reduces and dropout is
P D = (V IN – V OUT ) (I L )
The die temperature is dependent on both the ambient tempera-
ture and on the power being dissipated by the device. The inter-
nal die temperature must not exceed 125 ° C. Therefore, care
must be taken to ensure that, under normal operating condi-
tions, the die temperature is kept below the thermal limit.
T J = T A + P D ( θ JA )
–6 –
REV. A 0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP3367ARZ | 制造商:Analog Devices 功能描述:LDO 2.5-16.5V 0.3VDO 0.3A 8SOIC |
| ADP3367ARZ-REEL | 制造商:Analog Devices 功能描述:LDO Regulator Pos 1.3V to 16V5V 0.2A 8-Pin SOIC N T/R |
| ADP3367ARZ-REEL7 | 功能描述:IC REG LDO 5V/ADJ .2A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:800 系列:- 稳压器拓扑结构:正，固定式 输出电压:2.5V 输入电压:最高 16V 电压 - 压降（标准）:0.7V @ 4A 稳压器数量:1 电流 - 输出:4A 电流 - 限制（最小）:4.2A 工作温度:0°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-6，D²Pak（5 引线+接片），TO-263BA 供应商设备封装:TO-263-5 包装:带卷 (TR) 其它名称:AP1184K525L-13AP1184K525LDITR |
| ADP3401 | 制造商:AD 制造商全称:Analog Devices 功能描述:GSM Power Management System |
| ADP3401ARU | 制造商:AD 制造商全称:Analog Devices 功能描述:GSM Power Management System |
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