参数资料
| 型号： | ADP7102ARDZ-2.5-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/28页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 2.5V .3A 8SOIC |
| 标准包装： | 1,000 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 2.5V |
| 输入电压： | 3.3 V ~ 20 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 300mA（最小值） |
| 电流 - 限制（最小）： | 450mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 供应商设备封装： | 8-SOIC-EP |
| 包装： | 带卷 (TR) |
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Data Sheet
ABSOLUTE MAXIMUM RATINGS
ADP7102
Table 3.
Parameter
VIN to GND
VOUT to GND
EN/UVLO to GND
PG to GND
SENSE/ADJ to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
–0.3 V to +22 V
–0.3 V to +20 V
–0.3 V to VIN
–0.3 V to VIN
–0.3 V to VOUT
–65°C to +150°C
–40°C to +125°C
JEDEC J-STD-020
on PCB material, layout, and environmental conditions. The
specified values of θ JA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information on
the board construction. For additional information, see the
AN-617 Application Note, MicroCSP? Wafer Level Chip Scale
Package, available at www.analog.com .
Ψ JB is the junction-to-board thermal characterization parameter
with units of °C/W. The package’s Ψ JB is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP7102 can be damaged when the junction
temperature limit is exceeded. Monitoring ambient temperature
does not guarantee that T J is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low PCB
not the same as thermal resistances. Ψ JB measures the
component power flowing through multiple thermal paths
rather than a single path as in thermal resistance, θ JB . Therefore,
Ψ JB thermal paths include convection from the top of the
package as well as radiation from the package, factors that make
Ψ JB more useful in real-world applications. Maximum junction
temperature (T J ) is calculated from the board temperature (T B )
and power dissipation (P D ) using the formula
T J = T B + ( P D × Ψ JB )
See JESD51-8 and JESD51-12 for more detailed information
about Ψ JB .
Thermal Resistance
θ JA and Ψ JB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
θ JC is a parameter for surface-mount packages with top
mounted heatsinks. θ JC is presented here for reference only.
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T J ) of
the device is dependent on the ambient temperature (T A ), the
power dissipation of the device (P D ), and the junction-to-
Table 4. Thermal Resistance
Package Type θ JA
8-Lead LFCSP 40.1
8-Lead SOIC 48.5
θ JC
27.1
58.4
Ψ JB
17.2
31.3
Unit
°C/W
°C/W
ambient thermal resistance of the package (θ JA ).
Maximum junction temperature (T J ) is calculated from the
ESD CAUTION
ambient temperature (T A ) and power dissipation (P D ) using the
formula
T J = T A + ( P D × θ JA )
Junction-to-ambient thermal resistance (θ JA ) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ JA may vary, depending
Rev. C | Page 5 of 28
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相关代理商/技术参数 |
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| ADP7102ARDZ-3.0-R7 | 功能描述:IC REG LDO 3V .3A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 产品培训模块:More Information on LDOs 标准包装:50 系列:- 稳压器拓扑结构:正，固定式 输出电压:3.3V 输入电压:最高 15V 电压 - 压降（标准）:1.1V @ 800mA 稳压器数量:1 电流 - 输出:800mA 电流 - 限制（最小）:800mA 工作温度:0°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-4，D²Pak（3 引线+接片），TO-263AA 供应商设备封装:D2PAK-3 包装:管件 |
| ADP7102ARDZ-3.3-R7 | 功能描述:IC REG LDO 3.3V .3A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 产品培训模块:More Information on LDOs 标准包装:50 系列:- 稳压器拓扑结构:正，固定式 输出电压:3.3V 输入电压:最高 15V 电压 - 压降（标准）:1.1V @ 800mA 稳压器数量:1 电流 - 输出:800mA 电流 - 限制（最小）:800mA 工作温度:0°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-4，D²Pak（3 引线+接片），TO-263AA 供应商设备封装:D2PAK-3 包装:管件 |
| ADP7102ARDZ-5.0-R7 | 功能描述:IC REG LDO 5V .3A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 产品培训模块:More Information on LDOs 标准包装:50 系列:- 稳压器拓扑结构:正，固定式 输出电压:3.3V 输入电压:最高 15V 电压 - 压降（标准）:1.1V @ 800mA 稳压器数量:1 电流 - 输出:800mA 电流 - 限制（最小）:800mA 工作温度:0°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-4，D²Pak（3 引线+接片），TO-263AA 供应商设备封装:D2PAK-3 包装:管件 |
| ADP7102ARDZ-9.0-R7 | 功能描述:IC REG LDO 9V .3A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 产品培训模块:More Information on LDOs 标准包装:50 系列:- 稳压器拓扑结构:正，固定式 输出电压:3.3V 输入电压:最高 15V 电压 - 压降（标准）:1.1V @ 800mA 稳压器数量:1 电流 - 输出:800mA 电流 - 限制（最小）:800mA 工作温度:0°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-4，D²Pak（3 引线+接片），TO-263AA 供应商设备封装:D2PAK-3 包装:管件 |
| ADP7102ARDZ-R7 | 功能描述:IC REG LDO ADJ .3A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 产品培训模块:More Information on LDOs 标准包装:50 系列:- 稳压器拓扑结构:正，固定式 输出电压:3.3V 输入电压:最高 15V 电压 - 压降（标准）:1.1V @ 800mA 稳压器数量:1 电流 - 输出:800mA 电流 - 限制（最小）:800mA 工作温度:0°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-4，D²Pak（3 引线+接片），TO-263AA 供应商设备封装:D2PAK-3 包装:管件 |
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