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参数资料
| 型号： | ADRF6801ACPZ-R7 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 调制器/解调器 |
| 英文描述： | 750 MHz - 1150 MHz RF/MICROWAVE I/Q DEMODULATOR |
| 封装： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, CP-40-1, LFSCP_VQ, 40 PIN |
| 文件页数： | 15/36页 |
| 文件大小： | 1034K |
| 代理商： | ADRF6801ACPZ-R7 |
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ADRF6801
Rev. 0 | Page 22 of 36
I/Q OUTPUT CONNECTIONS
The ADRF6801 has I and Q baseband outputs. Each output
stage consists of emitter follower output transistors with a low
differential impedance of 24 Ω and can source up to 12 mA p-p
differentially. A Mini-Circuits TCM9-1+ balun is used to trans-
form a single-ended 50 Ω load impedance into a nominal 450 Ω
differential impedance.
RF INPUT CONNECTIONS
The ADRF6801 is to be driven single-ended and can be either dc
coupled or ac coupled. There is an on-chip ground referenced
balun that converts the applied single-ended signal to a differential
signal that is then input to the RF V-to-I converter.
CHARGE PUMP/VTUNE CONNECTIONS
The ADRF6801 uses a loop filter to create the VTUNE voltage
for the internal VCO. The loop filter in its simplest form is an
integrating capacitor. It converts the current mode error signal
coming out of the CPOUT pin into a voltage to control the VCO
via the VTUNE voltage. The stock filter on the evaluation
board has a bandwidth of 130 kHz. The loop filter contains
seven components, four capacitors, and three resistors. Changing
the values of these components changes the bandwidth of the loop
filter. Note that to obtain the approximately 2.5 kHz loop band-
width, the user can change the values of the following components
on the evaluation board to as follows: C14 = 0.1 μF, R10 = 68 Ω,
C15 = 4.7 μF, R9 = 270 Ω, C13 = 47 nF, R60 = 0 Ω, C4 = open.
LO SELECT INTERFACE
The ADRF6801 has the option of either monitoring a scaled
version of the internally generated LO (LOSEL pin driven high
at 3.3 V) or providing an external LO source (LOSEL pin driven
low to ground, the LDRV bit in Register 5 set low, and the LXL bit
in Register 5 set high). See the Pin Configuration and Function
Descriptions section for full operation details.
EXTERNAL LO INTERFACE
The ADRF6801 provides the option to use an external signal
source for the LO into the IQ demodulating mixer core. It is
important to note that the applied LO signal is divided down
by either 2 or 4 depending on the LO path divider bit, LDIV, in
Register 5, prior to the actual IQ demodulating mixer core. The
divider is determined by the register settings in the LO path
and mixer control register (see the Register 5—LO Path and
Demodulator Control section). The LO input pins (Pin 37 and
Pin 38) present a broadband differential 50 Ω input impedance.
The LOP and LON input pins must be ac-coupled. This is achieved
on the evaluation board via a Mini-Circuits TC1-1-13+ balun with
a 1:1 impedance ratio. When not in use, the LOP and LON pins
can be left unconnected.
SETTING THE FREQUENCY OF THE PLL
The frequency of the VCO/PLL, once locked, is governed by the
values programmed into the PLL registers, as follows:
fPLL = fPFD × 2 × (INT + FRAC/MOD)
where:
fPLL is the frequency at the VCO when the loop is locked.
fPFD is the frequency at the input of the phase frequency detector.
INT is the integer divide ratio programmed into Register 0.
MOD is the modulus divide ratio programmed into Register 1.
FRAC is the fractional value programmed into Register 2.
The practical lower limit of the reference input frequency is
determined by the combination of the desired fPLL and the maximum
programmable integer divide ratio of 119 and reference input
frequency multiplier of 2. For a maximum fPLL of 4600 MHz,
fREF > ~fPLL/(119 × 2 × 2), or 9.7 MHz.
A lock detect signal is available as one of the selectable outputs
through the MUXOUT pin, with logic high signifying that the
loop is locked.
When the internal VCO is used, the actual LO frequency is
fLO = fPLL/4
REGISTER PROGRAMMING
Because Register 6 controls the powering of the VCO and
charge pump, it must be programmed once before programming
the PLL frequency (Register 0, Register 1, and Register 2).
The registers should be programmed starting with the highest
register (Register 7) first and then sequentially down to Register 0
last. When Register 0, Register 1, or Register 2 is programmed,
an internal VCO calibration is initiated that must execute when
the other registers are set. Therefore, the order must be Register 7,
Register 6, Register 5, Register 4, Register 3, Register 2, Register 1,
and then Register 0. Whenever Register 0, Register 1, or Register 2
is written to, it initializes the VCO calibration (even if the value
in these registers does not change). After the device has been
powered up and the registers configured for the desired mode of
operation, only Register 0, Register 1, or Register 2 must be
programmed to change the LO frequency.
If none of the register values is changing from their defaults,
there is no need to program them.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADRF6801-EVALZ | 功能描述:EVAL BOARD FOR ADRF6801 制造商:analog devices inc. 系列:- 零件状态:有效 类型:解调器 频率:750MHz ~ 1.15GHz 配套使用产品/相关产品:ADRF6801 所含物品:板 标准包装:1 |
| ADRF6806ACPZ-R7 | 功能描述:IC QUADRATURE DEMOD 40LFCSP RoHS:是 类别:RF/IF 和 RFID >> RF 解调器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 功能:解调器 LO 频率:- RF 频率:70MHz ~ 300MHz P1dB:-9dBm 增益:- 噪音数据:6.36dB 电流 - 电源:41.5mA 电源电压:2.7 V 封装/外壳:28-WFQFN 裸露焊盘 供应商设备封装:28-TQFN-EP（5x5） 包装:带卷 (TR) |
| ADRF6806-EVALZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:EVAL 525MHZ QUAD DEMOD ADRF6806 制造商:Analog Devices 功能描述:ADRF6806, QUAD DEMOD, EVAL BOARD; Silicon Manufacturer:Analog Devices; Features:IQ Demodulator with Integrated Fractional-N PLL, Integrated PLL & VCO; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: Yes 制造商:Analog Devices 功能描述:MODULATOR/DEMODULATOR |
| ADRF6807 | 制造商:AD 制造商全称:Analog Devices 功能描述:700 MHz to 1050 MHz Quadrature |
| ADRF6807ACPZ-R7 | 功能描述:IC QUADRATURE DEMOD 40LFCSP RoHS:是 类别:RF/IF 和 RFID >> RF 解调器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 功能:解调器 LO 频率:- RF 频率:70MHz ~ 300MHz P1dB:-9dBm 增益:- 噪音数据:6.36dB 电流 - 电源:41.5mA 电源电压:2.7 V 封装/外壳:28-WFQFN 裸露焊盘 供应商设备封装:28-TQFN-EP（5x5） 包装:带卷 (TR) |
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