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参数资料
| 型号： | ADS1232REF |
| 厂商： | Texas Instruments |
| 文件页数： | 11/39页 |
| 文件大小： | 0K |
| 描述： | EVALUATION MODULE FOR ADS1232 |
| 产品培训模块： | Data Converter Basics |
| 视频文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 80 |
| 数据接口： | 串行 |
| 输入范围： | ±2.5 V |
| 在以下条件下的电源（标准）： | 7.1mW @ 5V |
| 工作温度： | -40°C ~ 105°C |
| 已用 IC / 零件： | ADS1232 |
| 已供物品： | 板 |
| 产品目录页面： | 889 (CN2011-ZH PDF) |
| 相关产品： | ADS1232IPWRG4-ND - IC ADC 24-BIT 10/80SPS 24-TSSOP 296-25894-2-ND - IC ADC 24-BIT 10/80SPS 24-TSSOP ADS1232IPWG4-ND - IC ADC 24-BIT 10/80SPS 24-TSSOP 296-18589-5-ND - IC ADC 24-BIT 10/80SPS 24-TSSOP |
| 其它名称： | 296-20803 |
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www.ti.com
DATA RETRIEVAL
DRDY/DOUT
23
22
21
1
24
0
LSB
MSB
Data
Data Ready
SCLK
t
2
t
7
t
3
t
3
t
6
New Data Ready
t
4
t
5
23
1
24
25
22
21
0
Data
25th SCLK to Force DRDY/DOUT High
Data Ready
New Data Ready
DRDY/DOUT
SCLK
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
indicating that new data are being updated. To avoid
having DRDY/DOUT remain in the state of the last
The ADS1232/4 continuously convert the analog
bit, the user can shift SCLK to force DRDY/DOUT
input signal. To retrieve data, wait until DRDY/DOUT
high, as shown in Figure 35. This technique is useful
goes low, as shown in Figure 34. After this occurs,
when
a
host
controlling
the
device
is
polling
begin shifting out the data by applying SCLKs. Data
DRDY/DOUT to determine when data are ready.
are shifted out MSB first. It is not required to shift out
all 24 bits of data, but the data must be retrieved
before new data are updated (within t7) or else it will
be overwritten. Avoid data retrieval during the update
period (t6). DRDY/DOUT remains at the state of the
last bit shifted out until it is taken high (see t6),
Figure 34. Data Retrieval Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t2
DRDY/DOUT low to first SCLK rising edge
0
ns
t3
SCLK positive or negative pulse width
100
ns
SCLK rising edge to new data bit valid: propagation
t4
50
ns
delay
t5
SCLK rising edge to old data bit valid: hold time
0
ns
t6
(1)
Data updating: no readback allowed
39
s
SPEED = 1
12.5
ms
t7
(1)
Conversion time (1/data rate)
SPEED = 0
100
ms
(1)
Values given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period.
Figure 35. Data Retrieval with DRDY/DOUT Forced High Afterwards
Copyright 2005–2008, Texas Instruments Incorporated
19
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADS1234 | 制造商:BB 制造商全称:BB 功能描述:Ultra Low-Noise, 24-Bit Analog-to-Digital Converter |
| ADS1234IPW | 功能描述:模数转换器 - ADC 24-Bit Ultra Low-Noise RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADS1234IPW | 制造商:Texas Instruments 功能描述:IC ADC ULTRALOW NOISE 24BIT SMD 制造商:Texas Instruments 功能描述:IC, ADC, ULTRALOW NOISE, 24BIT, SMD 制造商:Texas Instruments 功能描述:IC, ADC, ULTRALOW NOISE, 24BIT, SMD; Resolution (Bits):24bit; Sampling Rate:80SPS; Supply Voltage Min:2.7V; Supply Voltage Max:5.3V; Supply Current:1.35mA; Digital IC Case Style:TSSOP; No. of Pins:28; Input Channel Type:Differential;;RoHS Compliant: Yes |
| ADS1234IPWG4 | 功能描述:模数转换器 - ADC 24-Bit Ultra Low-Noise RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADS1234IPWR | 功能描述:模数转换器 - ADC 24-Bit Ultra Low-Noise RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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