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| 型号： | ADS6243IRGZT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 2-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC48 |
| 封装： | 7 X 7 MM, GREEN, PLASTIC, QFN-48 |
| 文件页数： | 17/76页 |
| 文件大小： | 3497K |
| 代理商： | ADS6243IRGZT |
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www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued)
PINS
NO.
I/O
OF
DESCRIPTION
NAME
NO.
PINS
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes
SCLK
34
I
1
(along with SDATA). See Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes
SDATA
33
I
1
(along with SCLK). See Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference modes. See
SEN
32
I
1
Table 6 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers through
hardware RESET by applying a high-going pulse on this pin or by using software reset
RESET
4
I
1
option. Refer to the Serial Interface section. In parallel interface mode, tie RESET
permanently high. (SCLK, SDATA and SEN function as parallel control pins in this mode).
The pin has an internal pull-down resistor to ground.
PDNA
31
I
1
Channel A ADC power down control pin.
PDNB
30
I
1
Channel B ADC power down control pin.
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection.
CFG1
23
I
1
See Table 9 for description.
Tie to AVDD for 2-wire interface with DDR bit clock.
Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture edge. See
CFG2
22
I
1
Table 10 for description.
For 12x serialization with DDR bit clock, tie to ground or AVDD.
CFG3
21
I
1
RESERVED pin - Tie to ground.
Parallel input pin. It controls data format and MSB or LSB first modes. See Table 12 for
CFG4
15
I
1
description.
Internal reference mode – common-mode voltage output
VCM
16
IO
1
External reference mode – reference input. The voltage forced on this pin sets the internal
reference.
OUTPUT PINS
DA0_P,DA0_M
47,48
O
2
Channel A differential LVDS data output pair, wire 0
DA1_P,DA1_M
45,46
O
2
Channel A differential LVDS data output pair, wire 1
DB0_P,DB0_M
39,40
O
2
Channel B differential LVDS data output pair, wire 0
DB1_P,DB1_M
37,38
O
2
Channel B differential LVDS data output pair, wire 1
DCLKP,DCLKM
43,44
O
2
Differential bit clock output pair
FCLKP,FCLKM
41,42
O
2
Differential frame clock output pair
NC
14
1
Do Not Connect
Connect to ground using multiple vias. Refer to Board Design Considerations in application
PAD
0
1
section.
24
Copyright 2007, Texas Instruments Incorporated
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