参数资料
型号: ADS62P42IRGCT
厂商: Texas Instruments
文件页数: 54/78页
文件大小: 0K
描述: IC ADC 14BIT DUAL 65MSPS 64-VQFN
产品培训模块: Data Converter Basics
标准包装: 1
位数: 14
采样率(每秒): 65M
数据接口: 串行,并联
转换器数目: 2
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘
供应商设备封装: 64-VQFN 裸露焊盘(9x9)
包装: 标准包装
输入数目和类型: 2 个差分,单极
其它名称: 296-23135-6
T0110-02
CLKOUTM
DA0(DB0)
DA2(DB2)
DA4(DB4)
DA6(DB6)
DA8(DB8)
DA10(DB10)
DA12(DB12)
D0
D2
D4
D6
D8
D10
D12
SampleN+1
SampleN
D0
D2
D4
D6
D8
D10
D12
D1
D3
D5
D7
D9
D11
D13
D1
D3
D5
D7
D9
D11
D13
CLKOUTP
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
Figure 96. DDR LVDS Interface
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100
, this results in a 350-mV
single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to
2.5 mA, 4.5 mA, and 1.75 mA ( LVDS CURRENT). In addition, there exists a current double mode, where this
current is doubled for the data and output clock buffers (register bits CURRENT DOUBLE).
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistances available are
–300 , 185 , and 150 (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistances. This results in eight effective terminations from open (no
termination) to 60
.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100
internal and 100- external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode. Figure 97 and Figure 98 compare the LVDS eye diagrams without and with 100-
internal termination.
With internal termination, the eye looks clean even with 10-pF load capacitance (from each output pin to ground).
The terminations can be programmed using register bits ( LVDS TERMINATION).
58
Copyright
2007–2012, Texas Instruments Incorporated
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